Shyju PV — CTO
Strategic, technical, and organizational leader with 25+ years of experience driving CPU performance analysis, CPU microarchitecture optimization, and power efficiency for flagship Mobile, Automotive, IoT, Wearables, and Compute platforms. Currently, I lead the CPUSS PnP (Performance and Power) charter for Snapdragon X Elite and custom CPU architectures at Qualcomm. I hold end-to-end ownership of the silicon lifecycle—from early performance modelling to post-silicon performance and power correlation, binning, and HVM readiness. My mission is surgically precise: ensuring every Snapdragon product hits the market with best-in-class power efficiency and a performance profile that defines industry standards. 🚀 CORE IMPACT & LEADERSHIP Snapdragon X Elite Delivery: Primary sign-off authority for CPU performance, frequency, and power, spanning pre-silicon targets through post-silicon validation. Proven Scale: Delivered 50+ SoCs across compute, auto, and mobile, achieving industry-leading Perf/W and a sustained <5% performance correlation. Organizational Growth: Built the BDC CPU Performance team from inception to 20+ specialized engineers, serving as the global technical authority for PnP sign-off. Executive Influence: Advise senior leadership on performance/power risks and binning strategies, shaping SKU positioning and OEM launch readiness. 🛠 TECHNICAL TOOLKIT CPU Performance & Benchmarking: Expert-level tuning and analysis using SPEC, Geekbench, Antutu, and custom workloads. CPU Microarchitecture: Deep knowledge of Custom & ARMv8/v9, Coherent Interconnects (NoC), DDR5/LPDDR5x, and Cache Hierarchies. Post-Silicon Engineering: Electrical characterization (IDDQ, Leakage, PVT), V-F Curve optimization, Vmin trade-offs, and ATE/SLT correlation to maximize silicon yields. PnP Methodology: Workload characterization, system-level tracing, DVFS, and BTO/MTO sign-off protocols. Software Systems: Linux/Android/Windows on ARM tuning, Energy Aware Scheduler (EAS), and compiler-level performance analysis. 💡 MISSION & STRATEGY I bridge the gap between engineering and product strategy. By establishing robust performance modelling and performance correlation strategies, I ensure pre-silicon targets translate into real-world wins. I work with ATE, SLT, and HVV teams to drive the best Vmin/Fmax and silicon yields, balancing aggressive performance bins with manufacturing stability.
Stackforce AI infers this person is a Semiconductor Performance Engineer with extensive experience in CPU architecture and benchmarking.
Location: Bengaluru, Karnataka, India
Experience: 24 yrs 6 mos
Skills
- Cpu Performance & Power Analysis
- Silicon Characterization
- Team Leadership
- Technical Authority
- Soc Performance Analysis
- Technical Leadership
- Cpuss Performance Analysis
- Pre-silicon Profiling
- Benchmarking Framework Development
- Performance Analysis
- Cryptographic Library Enhancement
- Network Security Protocols
Career Highlights
- Led performance analysis for Snapdragon X Elite.
- Built a high-performing CPU team at Qualcomm.
- Delivered 50+ SoCs with industry-leading performance.
Work Experience
Qualcomm
Principal Engineer, Manager (3 yrs 5 mos)
Senior Staff Engineer/ Manager (10 mos)
Senior Staff Engineer (4 yrs 2 mos)
Huawei Technologies
Senior System Architect (3 yrs 9 mos)
System Architect (11 mos)
System Architect (1 yr 2 mos)
Test System Architect (1 yr 1 mo)
ST-Ericsson
System Specialist (1 yr 4 mos)
STMicroelectronics
Sr Software Engineer (3 yrs 10 mos)
Software Engineer (1 yr 7 mos)
L&T Infotech
Software Engineer (8 mos)
CDAC (Former Electronics Research and Development Center of India - ER&DCI)
Research Associate (2 yrs 5 mos)
BPL Telecom
Design Engineer R&D (5 mos)
Education
Bachelor of Technology (B.Tech.) at University of Kerala