Shyju PV

CTO

Bengaluru, Karnataka, India24 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Led performance analysis for Snapdragon X Elite.
  • Built a high-performing CPU team at Qualcomm.
  • Delivered 50+ SoCs with industry-leading performance.
Stackforce AI infers this person is a Semiconductor Performance Engineer with extensive experience in CPU architecture and benchmarking.

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Skills

Core Skills

Cpu Performance & Power AnalysisSilicon CharacterizationTeam LeadershipTechnical AuthoritySoc Performance AnalysisTechnical LeadershipCpuss Performance AnalysisPre-silicon ProfilingBenchmarking Framework DevelopmentPerformance AnalysisCryptographic Library EnhancementNetwork Security Protocols

Other Skills

CPU Performance & BenchmarkingSilicon Yield OptimizationHVM ReadinessOrganizational GrowthWorkload analysisARM ArchitectureSoC Debug infrastructurePerformance estimationPerformance BenchmarkingBenchmarkingLinux Performance MonitoringStrategic PlanningCross-functional Team LeadershipArchitectural GovernanceSKU Strategy & Positioning

About

Strategic, technical, and organizational leader with 25+ years of experience driving CPU performance analysis, CPU microarchitecture optimization, and power efficiency for flagship Mobile, Automotive, IoT, Wearables, and Compute platforms. Currently, I lead the CPUSS PnP (Performance and Power) charter for Snapdragon X Elite and custom CPU architectures at Qualcomm. I hold end-to-end ownership of the silicon lifecycle—from early performance modelling to post-silicon performance and power correlation, binning, and HVM readiness. My mission is surgically precise: ensuring every Snapdragon product hits the market with best-in-class power efficiency and a performance profile that defines industry standards. 🚀 CORE IMPACT & LEADERSHIP Snapdragon X Elite Delivery: Primary sign-off authority for CPU performance, frequency, and power, spanning pre-silicon targets through post-silicon validation. Proven Scale: Delivered 50+ SoCs across compute, auto, and mobile, achieving industry-leading Perf/W and a sustained <5% performance correlation. Organizational Growth: Built the BDC CPU Performance team from inception to 20+ specialized engineers, serving as the global technical authority for PnP sign-off. Executive Influence: Advise senior leadership on performance/power risks and binning strategies, shaping SKU positioning and OEM launch readiness. 🛠 TECHNICAL TOOLKIT CPU Performance & Benchmarking: Expert-level tuning and analysis using SPEC, Geekbench, Antutu, and custom workloads. CPU Microarchitecture: Deep knowledge of Custom & ARMv8/v9, Coherent Interconnects (NoC), DDR5/LPDDR5x, and Cache Hierarchies. Post-Silicon Engineering: Electrical characterization (IDDQ, Leakage, PVT), V-F Curve optimization, Vmin trade-offs, and ATE/SLT correlation to maximize silicon yields. PnP Methodology: Workload characterization, system-level tracing, DVFS, and BTO/MTO sign-off protocols. Software Systems: Linux/Android/Windows on ARM tuning, Energy Aware Scheduler (EAS), and compiler-level performance analysis. 💡 MISSION & STRATEGY I bridge the gap between engineering and product strategy. By establishing robust performance modelling and performance correlation strategies, I ensure pre-silicon targets translate into real-world wins. I work with ATE, SLT, and HVV teams to drive the best Vmin/Fmax and silicon yields, balancing aggressive performance bins with manufacturing stability.

Experience

24 yrs 6 mos
Total Experience
3 yrs 6 mos
Average Tenure
8 yrs 5 mos
Current Experience

Qualcomm

3 roles

Principal Engineer, Manager

Promoted

Nov 2022Present · 3 yrs 5 mos

  • Key Responsibilities & Technical Leadership:
  • End-to-End PnP Governance: Serve as the primary sign-off authority for CPU Performance and Power (PnP) across the silicon lifecycle for Snapdragon X Elite and custom CPU architectures, encompassing BTO/MTO and ES/CS milestones.
  • Performance-Power Correlation: Drive technical strategy for pre-to-post silicon correlation, utilizing empirical models to achieve <5% variance across industry-standard suites (SPEC, Geekbench, Antutu).
  • Silicon Characterization & Binning: Collaborate with ATE, SLT, and HVV teams to establish IDDQ, leakage, and LPM correlations, optimizing the Vmin/Fmax envelope to maximize silicon yield while maintaining aggressive performance tiers.
  • Architectural Trade-off Analysis: Lead deep-dive "what-if" PPA analysis to influence CPU configuration, cache hierarchies, and coherent interconnect (NoC) scaling in partnership with PDM and Architecture teams.
  • System-Level Optimization: Oversee workload characterization and system-level tracing on Windows on ARM, Linux, and Android, optimizing DVFS, EAS (Energy Aware Scheduler), and compiler-level interactions.
  • Global Team Leadership: Founded and scaled the BDC CPU Performance organization to 20+ specialized engineers, establishing the technical standards for CPUSS validation across global sites.
  • HVM & SKU Strategy: Advise executive leadership on performance/power risk profiles to define competitive SKU positioning, binning strategies, and OEM launch readiness for 50+ SoCs.
  • Infrastructural Innovation: Architected a remote-access smart lab automation framework for parallel CPUSS experimentation, ensuring zero-downtime delivery of performance sign-offs.
Technical LeadershipCPU Performance & Power AnalysisSilicon Characterization

Senior Staff Engineer/ Manager

Jan 2022Nov 2022 · 10 mos

  • Working on Snapdragon Chipsets across Mobile and Adjacent markets.
Workload analysisARM ArchitectureTechnical LeadershipSoC Debug infrastructurePerformance estimationPerformance Benchmarking+1

Senior Staff Engineer

Oct 2017Dec 2021 · 4 yrs 2 mos

  • I am driving the charter for CPUSS performance analysis, modeling, pre-silicon profiling, and post-silicon correlation for snapdragon-based products.. In this capacity, I lead a high-performance team that delivers across business units.
Technical LeadershipCPUSS Performance AnalysisPre-Silicon Profiling

Huawei technologies

4 roles

Senior System Architect

Promoted

Jan 2014Oct 2017 · 3 yrs 9 mos

  • + Leading Caliper project, the benchmarking framework that generates a score based performance evaluation report for server platforms. (http://open-estuary.org/caliper-benchmarking)
  • + Server space performance analysis and benchmarking.
  • + Worked on Key CPU benchmarks and other system wide benchmarks.
  • + Analysis and system level debugging of SOC performance matrix (CPU, Cache,Memory, Storage, Network etc.) and application workload for ARM64 & Intel Xeon servers.
  • + Very good knowledge on Linux performance observation and monitoring tools and debugging techniques.
  • + Setup test farm/test bench and automation test suite to generate clear reports for stake holders and performance gap to SOC/Platform/Kernel teams.
  • + Reported plenty of bugs in ARM64 Estuary platform there by improving the ARM server platform delivery. (http://open-estuary.org)
  • + Maintainer of Caliper and top contributor for the same.(https://github.com/open-estuary/caliper)
  • + Communication,coordination and technical collaboration with multi site cross functional teams product improvement.
Technical LeadershipBenchmarking Framework DevelopmentPerformance Analysis

System Architect

Jan 2014Dec 2014 · 11 mos

  • + As a part of the network security team, enhancing and maintaining the cryptographic library of the network security protocols as per product requirements.
  • + Individual contributor responsible for interfacing with products and handling cryptographic requirements ranging from enhancing a current feature to implementation of a new cipher.
  • + Handled E2E requirements in block ciphers for network security protocols starting from customer interaction, design, development, coding and testing.
  • + Preside at software requirement and specification analysis, participate in performance coaching, technical interviews and technical review.
Technical LeadershipCryptographic Library EnhancementNetwork Security Protocols

System Architect

Apr 2012Jun 2013 · 1 yr 2 mos · Bangalore

  • + Seeded LKTL (Linux Kernel Test Lab) project and lead the same to qualify homegrown Kernels of Huawei.
  • + Proposed an automated build and test framework for various kernels. Analyzed test methodologies, tools, and framework for kernel testing(For example LTP and autotest)
  • + Open source collaboration and merge verification support for Kernel.
  • + Industry tool analysis for Linux kernel and recommendation to platform testing.
  • + Prepared product backlog and tracked program execution (Role of product owner and scrum master)
  • + Played role of product owner and scrum master in the project.

Test System Architect

Apr 2011May 2012 · 1 yr 1 mo · Bangalore

  • + As Techno manager and Test system architect for Linux platform delivery team, leading the test team for qualification of Linux distribution of customised WR and Suse kernels as per product requirements on multiple platforms.
  • + Interaction with customer and development teams to prepare the test strategy and test plan.
  • + Review test analysis and design from testers and ensure sufficiency of test cases.
  • + Identification of training needs and conducting training as per the requirements of the project .
  • + Interface to cross functional groups and stake holder management.
  • + Quality matrix, Test execution tracking and prepare version test report.

St-ericsson

System Specialist

Jan 2010May 2011 · 1 yr 4 mos · Bangalore

  • + Benchmarked & validated Linux & symbian releases for U8500. Worked on usecase modelling for mobile chipsets
  • + Experienced in designing and executing applications simulating various use cases on target boards (or virtual platforms) and evaluate performance (latency, MIPS, memory budget etc), in order to support prototyping of architectural concepts for existing or future chipsets.
  • + Interface with marketing and product definition teams to define enhanced use cases and expected performance on future platforms based on extrapolations of data gathered from use case analysis on existing platforms.
  • + Setup a lab with competitor platforms and delivered KPI based performance dash boards to access maturity

Stmicroelectronics

2 roles

Sr Software Engineer

Feb 2006Dec 2009 · 3 yrs 10 mos

  • + Build the benchmarking process (customised from normal test and integration methodology focusing on performance and system aspects to suite specifically for project requirements) from scratch .
  • + Setup the execution environment including purchase and configuration of the hardware and software tools.
  • + Responsible for interfacing with Business development, Technical marketing, Architecture team and Development community to tune the performance and highlighting the bottlenecks accessing the maturity of the platform.
  • + Designed board test package for reference boards and system verification strategies for embedded products.

Software Engineer

Jun 2004Jan 2006 · 1 yr 7 mos

  • + Development of test framework with Embedded GUI on Hardware Control Layer(HCL) for production board testing.
  • + Benchmark execution suite development.
  • + Preparation of Enhanced multimedia demo for Mobile world congress.
  • + Power and performance optimisation.
  • + L2 cache optimisation for ARM926EJ core.

L&t infotech

Software Engineer

Sep 2003May 2004 · 8 mos

  • + Worked on a MMI simulator on a windows platform for development of phone software executing on an ARM based platform (SAMSUNG’s SGH-E700/800).
  • + Experience in porting of RTK & the hardware dependent driver modules of target board on to the host side I/O through Semi hosting.
  • + Handled the design and development of memory and flash file system, System boot up sequence and display.

Cdac (former electronics research and development center of india - er&dci)

Research Associate

Mar 2001Aug 2003 · 2 yrs 5 mos · Trivandrum

  • + Developed channel encoding and burst formatting DSP algorithms for TETRA Base Station in C.
  • + Tested the above algorithms with TMS320c6416 using Code Composer Studio.
  • + C-code optimisation of the above algorithms for performance and execution speed.
  • + Involved in the interface design and integration of upper MAC and Lower MAC.
  • + Design and development of the Base Station Simulator (both on PC and on ARM based board) to support Call Registering, Call Set-up, Call maintenance, Speech Call and file transfer.
  • + Validation and testing of the Base Station and including active participation in integration, system testing and field trials.

Bpl telecom

Design Engineer R&D

Oct 2000Mar 2001 · 5 mos · Palakkad

  • Worked on Power Line Carrier Communication equipment (PLCC) which is one of the main products from BPL TELECOM. This is used in Electric power generating stations to send voice and data through the power lines. Responsible for the customisation and improvement of the individual components/modules.

Education

University of Kerala

Bachelor of Technology (B.Tech.) — Electronics and Communications Engineering

Jan 1996Jan 2000

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