Ishant Anand

Software Engineer

Hyderabad, Telangana, India10 yrs experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Static Timing Analysis for ASIC designs.
Led 13 successful tape-outs of SOC at advanced technology nodes.
Strong automation skills with scripting in multiple languages.

Stackforce AI infers this person is a Semiconductor expert specializing in ASIC design and Static Timing Analysis.

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Skills

Core Skills

Application-specific Integrated Circuits (asic)Static Timing Analysis

Other Skills

SynthesisAutomationPythonUNIX shellTCLPerlcshellSTA analysisTiming closureGUI tool developmentEquivalence checkDebuggingPython (Programming Language)CommunicationSkill Script

Experience

10 yrs

Total Experience

2 yrs 6 mos

Average Tenure

4 yrs 9 mos

Current Experience

Amd

2 roles

Member of Technical Staff

Jun 2025 – Present · 10 mos

Application-Specific Integrated Circuits (ASIC)

Senior STA Engineer

Jul 2021 – Present · 4 yrs 9 mos

Around 8 Years of Experience in IC engineering. hands-on experience in DFT , Synth & STA for low-power and high performance designs : 3nm - 7nm
Currently working as Timing lead STA Engineer at AMD, India.
Provide constraints for SCAN shift and scan capture mode to Physical Design Team.
Expertise in development of Full chip STA sign-off criteria, methodology, timing constraints & timing ECO flow.
Experience leading the execution to drive SoC STA closure for tape-out and supporting silicon debug.
Hands-on experience in Synthesis & Static Timing Analysis for low-power performance designs.
Experience in full chip timing sign-off checklist and overseeing final timing sign-off for ASICs.
Strong debugging skills- timing issues, SDC, clock propagation.
Efficient in automation through scripting with python, UNIX shell, TCL, Perl and cshell.
Mentoring the new members of the team to ensure successful Knowledge Transfer.
Have written many scripts to automate the timing analysis flow.
Part of 13 successful tape-outs of SOC at 3-5nm technology.

Application-Specific Integrated Circuits (ASIC)SynthesisStatic Timing AnalysisAutomationPythonUNIX shell+3

Mediatek

2 roles

Senior Design STA Engineer

Promoted

Jul 2019 – Jul 2021 · 2 yrs

Senior Design STA Engineer for multiple blocks in 6nm, 7nm projects.
Responsibilities:
Worked on STA analysis for 8+ ASIC projects in 7/6nm process nodes.
Good understanding of STA concepts related to Setup, Hold, Variation, Library LVF, SI Crosstalk/Noise, Constraints, Derates and SDF.
Worked on STA & Tweaker (For ECO cycles) tool closely with PD team for timing closure.
Developed a GUI tool for improving the efficiency in running and validating of synthesis & QC tools.
Developed a GUI tool for Design profiling and cell based analysis to improve the synthesis PPA( Power,
Performace, Area).

Application-Specific Integrated Circuits (ASIC)STA analysisTiming closureGUI tool development

Engineer

Jul 2018 – Jul 2019 · 1 yr

Design Backend Integration Engineer for multiple blocks in 6nm, 7nm projects.
Responsibilities:
Handled the full ownership of the block for timing closure (Physical MCMM Logic synthesis) and all QC checks (LEC, TMAX, STA, CDC).
Good experience in equivalence check and debugging NEQ.
Analysis and optimization of blocks for Latency, throughput, area and power to meet the designer specifications.
Worked on STA & Tweaker(For TECO cycles) tool closely with PD team for timing closure.

Application-Specific Integrated Circuits (ASIC)Timing closureEquivalence checkDebugging