Abhilash Srivastava

Software Engineer

Bengaluru, Karnataka, India8 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Over 7 years of experience in digital design and verification.
Expertise in validating complex TAP networks for CPUs.
Proven track record of improving MBIST IP based on customer feedback.

Stackforce AI infers this person is a Digital Design Engineer with expertise in DFT and validation in semiconductor industry.

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Skills

Core Skills

Digital DesignValidationMbist DevelopmentFront-end ValidationRtl DesignDft SolutionsSignal ProcessingControl SystemsSimulation

Other Skills

Scan validationTAP validationDebuggingCollaborationTestcase developmentMBIST IP developmentSafety feature testingNCSIM simulationSPYGLASSSYNTHESISFORMALITYTETRAMAXDiagnosis methodsCustomer supportDigital Sinewave Generator

About

I have over 7 years of experience working on digital design/verification. Currently, working as SOC DFT Engineer in Intel corporation and working on scan validation, also worked on TAP validation in the same team. Intel CPU contains a large number of JTAG TAPs and IJTAG registers and all the TAPs are connected in form of a network, I validate the TAP network whether all TAPs are functional, all its registers are working and also checks the securities. I worked as Senior Design Engineer in ST Microelectronics in past, developed and improved MBIST IP for our customers. I also gave support to the customers who were using our MBIST IP. I also did improvements in the MBIST IP by taking feedbacks from the customers. Most of the time, Challenges faced by the customers gave us the direction to improve IP. I was an intern in the same group earlier where I have worked on the high performance fully programmable digital sin gen design and ADC modeling. I have faced many challenges working on sine generator and these challenges make me good on designs. Fortunately, I had got the good silicon validated result of the sin gen by continuously working on them.

Experience

8 yrs 9 mos

Total Experience

2 yrs 11 mos

Average Tenure

4 yrs 3 mos

Current Experience

Intel corporation

SOC DFT Engineer

Jan 2022 – Present · 4 yrs 3 mos · Bengaluru, Karnataka, India

Validating CPU scan chain network, our goal is to make the scan chain network ready for actually ATPG pattern by validating lots of signal there.
Validating CPU TAP network which contains a large number of JTAG TAPs and IJTAG registers
Validating whether all TAPs are functional, all its Data/Instruction registers are working and also checks the securities.
Collaborate with RTL team to fix the debugged issue.
Developing/Updating testcases during validation if required.
Developing/Updating collaterals for validation if needed.
Debug the cases using Verdi tool.
Supporting internally to the DFX team if there is any issue related to TAP network.

Scan validationTAP validationDebuggingCollaborationTestcase developmentDigital Design+1

Stmicroelectronics

3 roles

Senior Design Engineer

Promoted

Nov 2020 – Jan 2022 · 1 yr 2 mos

Developing MBIST IP for different memory techno from 0.13 um to 28nm.
Working on adding the safety feature test in MBIST IP which can test the memory safety circuits.
Merging the different techno MBIST IP solution to a single IP solution.
Doing Front end validation of MBIST IP by running NCSIM simulation, SPYGLASS, SYNTHESIS, FORMALITY and TETRAMAX.
Added new approach to test the memory in which read and write happens in a single cycle.

MBIST IP developmentSafety feature testingNCSIM simulationSPYGLASSSYNTHESISFORMALITY+3

MBIST Design Engineer

Jun 2019 – Oct 2020 · 1 yr 4 mos

Working on RTL Design and development of Memory DFT solutions.
Developing repair Solutions for In-House ST memories.
Developing and improving diagnosis methods in MBIST IP.
Supporting customers.
Improving IP as per the customers feedbacks and our internal enhancements.

RTL DesignDFT solutionsDiagnosis methodsCustomer supportDFT Solutions

Internship Trainee

May 2018 – May 2019 · 1 yr

Worked on "High Performance Digital Sinewave Generator".
Developed a sine gen using an efficient algorithm to realize a sinusoidal oscillator in digital domain.
Constructed the design using a hybrid method of two very popular algorithm CORDIC and recursive to get sinusoid samples up to 4 GHz and also to get SFDR > 100 DB and SNR > 80 DB.
Scope was, first develop the hybrid approach using MATLAB thereafter implement rtl for the design using Verilog.
Real time behavior of the design is checked using FPGA Evaluation kit CMOD A7.
Also worked on SAR ADC functional modelling, completed 4 SAR ADC model delivery.
Due to working on design and modelling both, got the idea of different approaches of design and modelling.

Digital Sinewave GeneratorAlgorithm developmentRTL implementationFPGA evaluationDigital DesignSignal Processing

Defence research and development organisation (drdo)

Project Engineer

Aug 2015 – Jul 2017 · 1 yr 11 mos · Hyderbad

Having experience as a project engineer in Control System Laboratory, Research Centre Imarat,
DRDO ,Hyderabad as per the records from 1
st September 2015 to 27th July 2017. I did following tasks
in my job tenure.
Mathematical modeling and simulation of control system design of BLDC motor based EMA
(Electromechanical Actuation ) system.
Performance evaluation of actuation system including functional tests EMI/EMC and
environmental tests for various projects.

Mathematical modelingSimulationControl system designPerformance evaluationControl Systems