Jul 2013 – Feb 2019 · 5 yrs 7 mos

• Heading the pre-silicon & post-silicon validation and board design teams for Wearables and IOT platforms at Ineda.

Oct 2011 – Jun 2013 · 1 yr 8 mos

• Was leading SOC verification & validation activities during this period at Ineda.

Jun 2003 – Oct 2011 · 8 yrs 4 mos · Hyderabad Area, India

• Managed front-end activities for all the IP that was commonly used on multiple product lines of the Imaging and PC Media business unit. Successfully managed, built and led cross functional teams across multiple sites through production releases of the IPs.

Nov 1996 – May 2003 · 6 yrs 6 mos

• Lead two chip designs involving 4 million gates design each. Involved in the design and full-chip verification process from specification to tape-out of the Verilog RTL based on 10-Gigabit Ethernet, PCI, SONET and SPI-4 technologies targeted to applications for a RPR/SRP Metropolitan Area Network.
• FPGA Validation of 10-Gig Ethernet design in loop-back & back2back modes on Virtex-E FPGA.
• Lead and worked on Verilog and VHDL IP Core RTL designs and behavioral models based on USB, VFIR IrDA, I2C, PCI, AMBA AHB, VCI and Ethernet technologies.

May 1995 – Oct 1996 · 1 yr 5 mos

• Logic design of a router design and lab debug involving front-end ASIC design and analysis of field failures.
• Design owner of an I/O Controller board (Kaweah) used in a multiprocessor fault tolerant storage device system (Whitney).