Sanidhya Saxena

Software Engineer

Delhi, India5 yrs 7 mos experience

Key Highlights

  • Experienced in RTL Design for PCIe NoC Infrastructure.
  • Led Memory Subsystem design at NXP Semiconductors.
  • Strong foundation in Semiconductor Devices and Low-Power Designs.
Stackforce AI infers this person is a VLSI Design Engineer with expertise in semiconductor and embedded systems.

Contact

LinkedIn

Skills

Core Skills

Rtl DesignEmbedded SystemsDebugging

Other Skills

MicroArchitectureRTL CodingAnalog Circuit DesignEagle PCBLogistics ManagementElectronicsPublic RelationsMicrocontrollersDigital ElectronicsMicrosoft PowerPointArduino IDEMicrosoft OfficeMicrosoft ExcelAutodesk EAGLEArduino

About

Currently working as a PCIe IP RTL Design Engineer at Qualcomm. Ex-Digital Design Engineer (SoC Architect) at NXP Semiconductors India, where I led Memory Subsystem design, AHB Matrix implementation, System Controller, and Messaging Unit. Conducted full-chip RDC analysis and CRR. Conceptually strong in Semiconductor Devices, CMOS Digital Circuits, and Low-Power Designs. Eager for hands-on VLSI experience. MTech in Electronics System Engineering at IISc Bangalore. GATE AIR: 230 (EC, 2021) | Selected for BARC TSO at RRCAT, Indore. Fueled by innovation and a passion for electronics.

Experience

5 yrs 7 mos
Total Experience
1 yr 9 mos
Average Tenure
10 mos
Current Experience

Qualcomm

Engineer

Jul 2025 – Present · 10 mos · Bengaluru, Karnataka, India · On-site

  • Working on RTL Design and MicroArch for PCIe NoC Infrastructure.
RTL DesignMicroArchitectureEmbedded Systems

Nxp semiconductors

SoC Architect

Jul 2022 – Aug 2023 · 1 yr 1 mo · Noida, Uttar Pradesh, India

  • Worked on designing and debugging of following modules:
  • 1) AMBA AHB Bus matrix RTL and its verification
  • 2) Memory controller and BIST logic integration
  • 3) Messaging unit for communication between multiple cores.
  • Few custom logics like Reset controller, BGR trim load logic was designed
  • Few SOC level flows under my ownership:
  • 1) RDC (Reset Domain Crossing)
  • 2) CRR (Common Register Repository)
RTL CodingDebuggingRTL Design

Texas instruments

Validation Engineer

May 2021 – Jul 2021 · 2 mos · Bangalore Urban, Karnataka, India

Tech swarm

Embedded System Developer

Jul 2020 – Jul 2022 · 2 yrs · New Delhi, Delhi, India

Ieee

2 roles

General secretary

May 2020 – Jul 2021 · 1 yr 2 mos

Joint Secretary

Apr 2019 – May 2020 · 1 yr 1 mo

Coding club

learner

Nov 2018 – Jul 2020 · 1 yr 8 mos · new delhi dwarka

Education

Indian Institute of Science (IISc)

Master of Technology - MTech — Electronics Systems and Engineering

Aug 2023 – Aug 2025

Netaji Subhas Institute of Technology

Bachelor of Engineering - BE

Jan 2018 – Jan 2022

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