Kiran Tholu

Product Engineer

Hyderabad, Telangana, India21 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • 19 years of experience in VLSI Design and management.
  • Proven track record in multiple tape-outs and Soft IP productization.
  • Expertise in FPGA IPs and ASIC designs across various domains.
Stackforce AI infers this person is a VLSI Design expert with extensive experience in semiconductor and FPGA industries.

Contact

Skills

Core Skills

Silicon ValidationRtl DevelopmentTechnical LeadershipQuality AssuranceProject Management

Other Skills

RDMAField-Programmable Gate Arrays (FPGA)TapeoutApplication-Specific Integrated Circuits (ASIC)System on a Chip (SoC)ArchitectureMicroarchitectureproject managamentFPGA prototypingProductizationManaging Technical PersonnelHands-on Technical LeadershipEthernetCarrier EthernetNetwork Switches

About

VLSI Design professional with 19 years of extensive experience in project and team management, Architecture, Design and Quality Assurance of FPGA IPs and ASIC designs. Proven track record in multiple tape-outs and Soft IP productization across various domains, including data centres, storage, networking, and SoCs. Experienced in Architecture, Microarchitecture, RTL design, Post-silicon validation, Prototyping, and DV using SystemVerilog (SV) OVM/UVM. ASIC / FPGA / SoC Publication: https://ieeexplore.ieee.org/document/8056743 MEF CECP 2.0 certified. Projects include: High B/W switching, RDMA, 10, 25, 40, 50 & 100G Ethernet, IEEE1588, MACSec, 10GE Mappers, L2 Switching.

Experience

21 yrs 4 mos
Total Experience
3 yrs 3 mos
Average Tenure
8 yrs 2 mos
Current Experience

Amd

SMTS Silicon Design Engineer

Mar 2018Present · 8 yrs 2 mos · Greater Hyderabad Area · On-site

RDMAField-Programmable Gate Arrays (FPGA)Silicon ValidationTapeoutApplication-Specific Integrated Circuits (ASIC)System on a Chip (SoC)+3

Synopsys inc

ASIC Digital Design Engineer Sr II

Sep 2017Mar 2018 · 6 mos · Greater Hyderabad Area

Intel corporation

SMTS IP Design at Intel-PSG

Jan 2016Sep 2017 · 1 yr 8 mos · Penang, Malaysia

project managamentTechnical LeadershipField-Programmable Gate Arrays (FPGA)FPGA prototypingProductizationQuality Assurance

Synaptics

Staff Verification Engineer

Sep 2015Dec 2015 · 3 mos · Greater Hyderabad Area

  • SV-VMM Based Verificaiton, Technical Lead

Vitesse semiconductor

2 roles

Sr MTS

Promoted

Nov 2007Aug 2015 · 7 yrs 9 mos

Project ManagementManaging Technical PersonnelHands-on Technical LeadershipEthernetCarrier EthernetNetwork Switches+4

MTS

Jan 2007Jan 2013 · 6 yrs

Qualcore logic ltd

Member of Technical Staff

Jul 2005Oct 2007 · 2 yrs 3 mos

  • RTL Design, Verification, DFT, Synthesis, GateLevel Simulation.
  • Joined Nuelight in July2005. Nuelight is absorbed into Qualcore in May 2006. At Nuelight worked on Design, Verification, Validation, FPGA

Nuelight corp

Design Engineer

Jul 2005Apr 2006 · 9 mos · Greater Hyderabad Area

Cmc ltd

Trainee

Jul 2004Jun 2005 · 11 mos

Education

Jawaharlal Nehru Technological University

Master of Technology - MTech — VLSI System Design

Jan 2003Jan 2005

Jawaharlal Nehru Technological University

Bachelor of Technology - BTech — Electircal and Electronics Engineering

Jan 1999Jan 2003

Narayana Junior college

Intermediate — MPC

Jan 1997Jan 1999

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