Kiran Tholu — Product Engineer
VLSI Design professional with 19 years of extensive experience in project and team management, Architecture, Design and Quality Assurance of FPGA IPs and ASIC designs. Proven track record in multiple tape-outs and Soft IP productization across various domains, including data centres, storage, networking, and SoCs. Experienced in Architecture, Microarchitecture, RTL design, Post-silicon validation, Prototyping, and DV using SystemVerilog (SV) OVM/UVM. ASIC / FPGA / SoC Publication: https://ieeexplore.ieee.org/document/8056743 MEF CECP 2.0 certified. Projects include: High B/W switching, RDMA, 10, 25, 40, 50 & 100G Ethernet, IEEE1588, MACSec, 10GE Mappers, L2 Switching.
Stackforce AI infers this person is a VLSI Design expert with extensive experience in semiconductor and FPGA industries.
Location: Hyderabad, Telangana, India
Experience: 21 yrs 4 mos
Skills
- Silicon Validation
- Rtl Development
- Technical Leadership
- Quality Assurance
- Project Management
Career Highlights
- 19 years of experience in VLSI Design and management.
- Proven track record in multiple tape-outs and Soft IP productization.
- Expertise in FPGA IPs and ASIC designs across various domains.
Work Experience
AMD
SMTS Silicon Design Engineer (8 yrs 2 mos)
Synopsys Inc
ASIC Digital Design Engineer Sr II (6 mos)
Intel Corporation
SMTS IP Design at Intel-PSG (1 yr 8 mos)
Synaptics
Staff Verification Engineer (3 mos)
Vitesse Semiconductor
Sr MTS (7 yrs 9 mos)
MTS (6 yrs)
Qualcore Logic ltd
Member of Technical Staff (2 yrs 3 mos)
Nuelight Corp
Design Engineer (9 mos)
CMC Ltd
Trainee (11 mos)
Education
Master of Technology - MTech at Jawaharlal Nehru Technological University
Bachelor of Technology - BTech at Jawaharlal Nehru Technological University
Intermediate at Narayana Junior college