Asha Gummadidala — Software Engineer

I have 2+ years of Experience as Analog Design Engineer from ChipEx Technologies. Proficient in using cadence virtuoso (ADE XL and maestro) pre layout simulations and design extraction (RC Extraction) to analyze parasitics after the layout (post layout simulations). Ability to analyze Electrical specifications and create test benches to test functionality and meet the required specifications. Experience in DC, Trans, AC,STB analysis PVT simulations and monte Carlo simulations. Familiar with windows and Linux. Designed all the basic logic gates(NAND, NOR, AND, OR, XOR, XNOR, AOI, OAI, MUX and DEMUX). Designed different full adders like Ripple carry adder, carry look ahead adder and carry select adder. Designed dynamic D flip flop. Designed D flip flop for high speed with minimum setup time and tcq. Clocked cmos is used in the design of latches. Maximum frequency of operation is achieved at slow corner. Hands on experience in designing basic blocks like SERIALIZER 2X1 , SERIALIZER 4X1, DESERIALIZER 1X2 and DESERIALIZER 1X4. Implemented Current mirror with multiple outputs design for the given specifications. PVT and monte Carlo simulations are done. Systematic and random mismatch are measured. Designed Nmos differential pair with Pmos active load for given specifications. Designed and simulated LDO. Checked simulations for line and load regulations measured on dc simulation. Checked simulations for line and load regulations measured on transient simulation. PSRR is measured. Designed voltage to current converter. Checked simulations for DC, trans, AC and STB analysis. RC compensation is used to achieve stability. Minimum 60 degree PM is achieved across corners. Designed two stage unity gain op amp(pmos differential pair+NMOS CS Amplifier). Designed hysteresis comparator with two stage op amp.

Stackforce AI infers this person is a skilled Analog Design Engineer with expertise in circuit simulation and design.

Experience: 2 yrs 5 mos