Tanuj Jindal

Software Engineer

Bengaluru, Karnataka, India17 yrs 6 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in Physical Design and Static Timing Analysis.
Achieved significant resource efficiency and PPA savings.
Recognized for technical excellence across multiple projects.

Stackforce AI infers this person is a Semiconductor Engineering expert with a focus on Physical Design and Timing Analysis.

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Skills

Core Skills

Physical DesignAutomationStatic Timing Analysis

Other Skills

DebugTechnical LeadershipCoachingVLSIPrimetimeDebuggingSimulationsVerilogEDAAlgorithmsHardware ArchitectureMicroprocessorsSemiconductorsComputer ArchitectureLogic Design

About

Key strength: Immediate productivity, Inclination for efficiency improvement, Excellent Cross domain knowledge, debug and correlation capabilities. Technical expertise lies in Static Timing Analysis, Automation, Debug, Design Planning, Physical Design, Clocking and ability to correlate various aspects from RTL to GDS design for better PPA. Relevant Programming / Tools: C , C++ , TCL , Perl , Verilog , HSPICE , Design Compiler , PrimeTime , Fusion Compiler, ICC*, LEC , Virtuoso , Tango (Device / Std Cell Timing Analysis), Scarlet (RC extraction), Presto (Circuit simulation).

Experience

17 yrs 6 mos

Total Experience

3 yrs 6 mos

Average Tenure

11 yrs 6 mos

Current Experience

Intel corporation

3 roles

Principal Engineer

Promoted

Mar 2024 – Present · 2 yrs 1 mo

SoC Physical Design/Timing Lead Engineer

Promoted

May 2019 – Mar 2024 · 4 yrs 10 mos

Tech Lead / innovator for all domains related to Physical Design in Graphics Team.
Achievements:
a) Selected for 2nd Best Technical Presentation as part of "Technical Showcase-2nd edition" across whole Graphics Organization (including FE/Arch/SD/Val)
b) Developed infrastructure to enable PPA optimized, consistent and predictable FP pin placement across all milestones and architectures for GT IP. TAT for stable FP reduced from weeks to 1 day.
c) ~50% resource efficiency and significant PPA saving as part of latest integrated graphics execution.
d) Physical Design Lead for the leading Integrated Graphics IP.
e) Complete ownership of repeater planning and execution across the owned Graphics IP.
f) Drove Sign-Off activities for Cross Voltage STA across multiple programs.
HBMIO IP Execution Lead:
a) Worked on defining the Floorplan, Bump Map, Power Plan and Metal Grid.
b) Drove the Physical Design / Timing closure activity through contract workers.

Physical DesignAutomation

Physical Design and Timing Engineer

Sep 2014 – Apr 2019 · 4 yrs 7 mos

Worked in an environment providing exposure to challenges in high speed IP design. IP's containing mix of PnR + Custom Digital + Mixed Signal environment.
In this role I have been exposed to 3 different HS architecture: KTI/UPI (HSIO), OPIO/RLINK and DDR.
Accomplishments:
1. Reduced Scan Buffer insertion by 50% by implementing an algorithm to give correct by construction scan hook up from post functional fixes. This work was also selected as one of 250 presentation for the Technical Conference across whole Intel.
2. Cross domain understanding of Circuit along with SD helped in smooth cross team interaction and faster closure cycle.
3. Extremely low clock latency achieved as part of ICC implementation in one of the blocks during RLINK execution.

Broadcom

2 roles

Senior Staff Engineer

Feb 2014 – Aug 2014 · 6 mos

Multiple block synthesis, Timing/Noise analysis. Maintaining/developing timing flows and methodology.

Staff II- IC Design

Jan 2013 – Jan 2014 · 1 yr

Major work included correlating PrimeTime with GoldTime.
Migrated the full flow (scripts/report generation/feature definition) into PrimeTime.

Intel corporation

Component Design Engineer

Sep 2010 – Nov 2012 · 2 yrs 2 mos · Portland, Oregon Area

Owner of Extraction / Static Timing Analysis (Device Level and Standard Cell) in Advanced Design Group. Also actively involved in debug and resolving issue related to Circuit Simulation and RV analysis.
Significant contribution in methodology development for extraction/timing friendly layout generation.

Advanced micro devices

Intern

Jan 2010 – May 2010 · 4 mos

1. Created a unified logical templates for Noise analysis.
2. Developed various algorithms for Low Power analysis and estimation.

Texas instruments

Design Engineer

Jul 2006 – Jul 2008 · 2 yrs

Design Engineer, Wireless Division
.
Major Focus on Synthesis, Formal Verification, DRC checks & Static Timing Analysis. Hands on Experience with RDL routing, Floorplanning and Power Planning.
Sole ownership of Synthesis, Equivalence check and Static Timing Analysis in 65nm design.
Achieved run time reduction of 4 hours and significant area gain in synthesis.
Developed complex IO multiplexing constraints efficiently in just 4 days.