Rakesh Kumar

DevOps Engineer

Bengaluru, Karnataka, India16 yrs 7 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in Physical Design and ASIC development.
  • Proven track record in standard cell library characterization.
  • Strong background in semiconductor engineering.
Stackforce AI infers this person is a semiconductor engineering expert with a focus on ASIC and physical design.

Contact

LinkedIn

Skills

Core Skills

Physical DesignAsicStandard Cell CharacterizationStandard Cell Library CharacterizationIntegrated CircuitsCmos Integrated Circuit Design

Other Skills

Central EngineeringFlow developmentLibQAIP physical verificationStd. Cell Library developmentCharacterizationCircuit designLayout designStd. Cell Library characterizationStd cell circuit designVLSIIntegrated Circuit DesignICSemiconductorsCadence Virtuoso

About

Experienced Staff Design Engineer with a demonstrated history of working in the semiconductors industry. Strong engineering professional skilled in Physical Design, Central engineering, Standard Cell library Characterization, Application-Specific Integrated Circuits (ASIC), Integrated Circuits (IC), CMOS Integrated Circuit Design, and Semiconductors.

Experience

16 yrs 7 mos
Total Experience
3 yrs 3 mos
Average Tenure
3 yrs 10 mos
Current Experience

Intel corporation

CPU Physical design

Jul 2022 – Present · 3 yrs 10 mos · Bengaluru, Karnataka, India

Apex semiconductor

Sr. Staff Design Engineer

Feb 2019 – Jun 2022 · 3 yrs 4 mos · India

  • Physical design, Central Engineering and Flow development, LibQA, IP physical verification.
Physical designCentral EngineeringFlow developmentLibQAIP physical verificationPhysical Design+1

Appliedmicro

Staff Design Engineer

Jun 2015 – Feb 2019 · 3 yrs 8 mos · Pune Area, India

  • Physical design, Central Engineering, Standard cell characterization, LibQA, IP physical verification.
Physical designCentral EngineeringStandard cell characterizationLibQAIP physical verificationPhysical Design+1

Stmicroelectronics

Senior Design Engineer

Apr 2010 – Jun 2015 · 5 yrs 2 mos · Noida Area, India

  • Std. Cell Library development and characterization. ckt and layout design.
Std. Cell Library developmentCharacterizationCircuit designLayout designStandard Cell Library CharacterizationIntegrated Circuits

Rf silicon pvt. ltd

Design Engineer

Aug 2009 – Mar 2010 · 7 mos

  • Std. Cell Library characterization, Std cell circuit and layout design.
Std. Cell Library characterizationStd cell circuit designLayout designStandard Cell CharacterizationCMOS Integrated Circuit Design

Education

Panjab University

M.Tech — Microelectronics

Jan 2007 – Jan 2009

Kurukshetra University

M.Sc — Electronics

Jan 2005 – Jan 2007

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