SAT PRAKASH

Software Engineer

Bengaluru, Karnataka, India6 yrs 9 mos experience

Highly Stable

Key Highlights

3+ years in RTL Design and Verification.
Expertise in DFT pattern generation for High-Speed IO interfaces.
Proficient in Verilog and System Verilog.

Stackforce AI infers this person is a specialist in ASIC design and verification within the semiconductor industry.

Contact

Skills

Core Skills

Rtl DesignDft

Other Skills

Digital DesignVerilogBIST DesignCDC and SynthesisSystem VerilogRTL and Gate Level Simulation and DebugFullChip VerificationIO-BIST Pattern GenerationSilicon DebugATE TesterDigital Circuit DesignApplication-Specific Integrated Circuits (ASIC)Front-End DevelopmentTest CoverageVectors

About

3+ years of experience in RTL Design/Verification and DFT pattern generation for BIST for various High-Speed IO interface like lpddr5x, m-phy and eMMC. SKILLS : RTL : Digital Design | Verilog | BIST Design | CDC and Synthesis | Exposure to lpddr5x, mipi-MPHY and eMMC protocols. Verification : System Verilog | RTL and Gate Level Simulation and Debug | FullChip Verification DFT : IO-BIST Pattern Generation | Silicon Debug | ATE Tester

Experience

6 yrs 9 mos

Total Experience

6 yrs 9 mos

Average Tenure

6 yrs 9 mos

Current Experience

Nvidia

2 roles

Senior ASIC Engineer

Promoted

Jun 2022 – Present · 3 yrs 10 mos

3+ years of experience in RTL Design/Verification and DFT pattern generation for BIST for various High-Speed IO interface like lpddr5x, m-phy and eMMC.
SKILLS :
RTL : Digital Design | Verilog | BIST Design | CDC and Synthesis | Exposure to lpddr5x, mipi-MPHY and
eMMC protocols.
Verification : System Verilog | RTL and Gate Level Simulation and Debug | FullChip Verification
DFT : IO-BIST Pattern Generation | Silicon Debug | ATE Teste

Digital DesignVerilogBIST DesignCDC and SynthesisSystem VerilogRTL and Gate Level Simulation and Debug+6