Naveen Kanumuri

DevOps Engineer

Noida, Uttar Pradesh, India25 yrs 11 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expertise in SoC architecture and design.
  • Proven track record in low power design methodologies.
  • Strong background in functional verification and debugging.
Stackforce AI infers this person is a semiconductor design expert with a focus on SoC architecture and low power design.

Contact

LinkedIn

Skills

Other Skills

SoCICSemiconductorsASICRTL designLow Power DesignFunctional VerificationSpecmanDebuggingFPGAVerilogLogic SynthesisVLSILow Power VerificationCMOS

Experience

25 yrs 11 mos
Total Experience
5 yrs 2 mos
Average Tenure
11 yrs 5 mos
Current Experience

Intel corporation

2 roles

SoC Functional Safety Architect

Promoted

Dec 2021 – Present · 4 yrs 4 mos · Bengaluru, Karnataka, India · On-site

IP Architect

Oct 2014 – Nov 2021 · 7 yrs 1 mo · Bengaluru, Karnataka, India · On-site

Ericsson

Principal Engineer, SoC Architect

Aug 2013 – Oct 2014 · 1 yr 2 mos · Bengaluru, Karnataka, India · On-site

Stmicroelectronics

3 roles

Member of Technical Staff

Jul 2009 – Jul 2013 · 4 yrs

Project Leader

Promoted

Jan 2008 – Jun 2009 · 1 yr 5 mos

Senior Design Engineer

Jun 2003 – Dec 2007 · 4 yrs 6 mos

Philips semiconductors

2 roles

Design Engineer

Mar 2001 – Dec 2002 · 1 yr 9 mos

Engineering Intern

Apr 2000 – Dec 2000 · 8 mos

Ramco systems

Analyst Programmer

Jun 1998 – Jun 1999 · 1 yr

Education

Arizona State University

MS — Solid State Electronics

Jan 1999 – Jan 2000

PSG College of Technology

BE — Electronics and Electrical Engineering

Jan 1994 – Jan 1998

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