Amit R — Product Manager

Core competencies - ► Total 7+year of experience in Physical Design and Synthesis and STA. Knowledge of ASIC Physical Design Flow, APR Flow, Logic Synthesis, Static Timing Analysis, Floor planning, Power Planning, Placement, CTS, Routing ,ECO,DRC, LVS, PV. Client worked- Qualcomm, NXP, STM. ► Experience on 3nm,4nm,5nm,10nm,14nm,16nm,28nm technology on Synopsys IC Compiler, Innovus,STAR-RC and Prime Time Tools. ► Experience on Synthesis,Floor planning, Power plan, Placement, Place and route, Clock tree synthesis, Power / IR Drop /EM analysis, Routing and completed 3 projects on single as well as multi voltage domain. ► Generated SPEF by STAR-RC and Analysed Timing Reports generated by Prime Time & ICC & finding the ways to solve the violations as a part of STA. ► Power Planning with a number of iterations by setting different metal width and number of tracks to get IR Drop and EM within the target. ► Analysed Congestion after placement & reduced it using different ways. ► knowledge on scripting using Perl & TCL. ► Programming Languages: C, C++, Verilog. ► Completed Technical Course in VLSI Physical Design (Duration - 6+months) and expertise in block level implementation from Netlist to GDSII with various projects at 28nm Technology on Synopsys ICC/ICC2, StarRC and Prime time tools.

Stackforce AI infers this person is a VLSI Design Engineer with expertise in Physical Design and Static Timing Analysis.

Location: Bengaluru, Karnataka, India

Experience: 8 yrs 4 mos