Shivam Singal

Engineering Manager

Bengaluru, Karnataka, India15 yrs 1 mo experience

Highly Stable

Key Highlights

Led advancements in high-speed interface technologies.
Validated CXL1.1 protocol in collaboration with global leaders.
Developed PCIe validation strategies for cutting-edge products.

Stackforce AI infers this person is a Semiconductor Engineering Manager with expertise in high-speed interfaces and ASIC development.

Contact

Skills

Core Skills

High Speed InterfacesSilicon ValidationPcieQuick Path Interconnect

Other Skills

Validation StrategyValidationManagement ProfessionalProcessorsX86Cross-functional Team LeadershipMicroprocessorsx86 AssemblyTechnical LeadershipIA32Cache CoherencyIA64DebuggingC/C++ STLEclipse

About

As an Engineering Manager at NVIDIA, my recent endeavors include spearheading advancements in high-speed interface technologies such as PCIe, NVLINK, particularly the validation of the C2C-Chip to Chip protocol. With a focus on ASIC development, my stewardship has empowered our team to achieve breakthroughs in enhancing system interconnectivity. My leadership is further characterized by a commitment to fostering cross-site collaborations and engaging with global leaders, which culminates in the delivery of pioneering products. Our approach is shaped by a synthesis of technical prowess in ASIC and high-speed interfaces, ensuring our solutions meet the rigorous standards of the tech industry.

Experience

15 yrs 1 mo

Total Experience

9 yrs 11 mos

Average Tenure

5 yrs 2 mos

Current Experience

Nvidia

2 roles

Engineering Manager

Apr 2024 – Present · 2 yrs

High Speed InterfacesSilicon Validation

Senior Staff Engineer

Feb 2021 – Apr 2024 · 3 yrs 2 mos

Silicon Solutions Group - High Speed Interconnect

Intel corporation

3 roles

Engineering Manager

Promoted

Apr 2019 – Feb 2021 · 1 yr 10 mos

1) Validated CXL1.1 protocol (Compute Express Link) in between FPGA and Xeon CPU in Post Silicon profile.
2) Participated in multiple power-ons happened across Santa Clara, US and Austin, US. - Been in US for 3 months for the same and have good exposure of working cross site and with global leaders.

Technical Team Lead

Promoted

Nov 2015 – Mar 2019 · 3 yrs 4 mos

1) Validated Gen3/Gen4 PCIe IP over Ethernet Based Products.
2) Did multiple Power-Ons in Bangalore and Israel(Jeruselam/ Haifa) lab.
3) Travelled to various PCIe-Sig Conferences - For Compliance Certifications across Taiwan (The Westin Taipei - PCI-SIG Compliance Workshop #103/ #107) and California, US (Embassy Suites Burlingame - PCI-SIG Compliance Workshop #108)
4) Created PCIe Gen4 Validation Strategy along with Intel Phoenix, Arizona counter parts - travelled to present my work.

System Validation Engineer

Jan 2011 – Oct 2015 · 4 yrs 9 mos

Validate the Quick Path Interconnect protocol in multi Xeon Server CPU environment for INTEL's next generation state-of-the-art CPUs in the Post-Si Environment!!
Presented multiple Technical Papers in DTTC, Oregon, US.