Venkata sandeep S.

Software Engineer

United States5 yrs 5 mos experience
Highly StableAI Enabled

Key Highlights

  • Expert in SOC Design and Verification.
  • Proficient in PCIe and CXL protocols.
  • Strong experience across multiple Intel sites.
Stackforce AI infers this person is a Semiconductor and Data Center Verification Engineer with extensive experience in SOC design.

Contact

LinkedIn

Skills

Core Skills

System On A Chip (soc)Functional Verification

Other Skills

1G Ethernet portAI switchASICCC++CXLDebuggingEmulationEthernetFormal VerificationJavaMatlabMicrosoft OfficePCIEPCIe

About

I'm a savvy, results-oriented SOC Design/Verification Engineer with an outstanding experience in Peripherals I/O like PCIE up to GEN-6 , CXL1.0 protocols I like to build scratch level verification environment and test scenarios which provide logical solutions to Complex SOC problems. My primary skill is getting things done. I am not hesitant to learn and unlearn stuff to accomplish tasks. I do not limit myself to the Front end domain, have experience in supporting post-silicon teams, emulation teams, and Back end teams across different sites of INTEL like Folsom, Santa Clara, Oregon, Penang, Munich, Haifa. šŸ‡µšŸ‡¹āš½. Your love makes me strong, your hate makes me unstoppable. Crsevenfanforever

Experience

Microchip technology inc.

senior soc design verification Engineer

Aug 2022 ā€“ Present Ā· 3 yrs 7 mos Ā· Oregon, United States Ā· Remote

  • Working on CXL and Pcie advanced AI switch šŸŽ›ļø support more than 100 lanes for AI data center application
CXLPCIeAI switchSystem on a Chip (SoC)Functional Verification

Apple

Design and verification engineer

Mar 2021 ā€“ Jul 2022 Ā· 1 yr 4 mos Ā· Oregon, United States Ā· On-site

  • Worked on Unit level verification of IP support for power management applications on šŸŽ next generation devices šŸ’»šŸ“±āŒšļø
Unit level verificationPower management applicationsFunctional VerificationSystem on a Chip (SoC)

Intel corporation

2 roles

Graduate Technical Intern

Jun 2020 ā€“ Aug 2020 Ā· 2 mos Ā· Portland, Oregon, United States

soc verification Engineer

Jul 2015 ā€“ Aug 2019 Ā· 4 yrs 1 mo Ā· Bengaluru, Karnataka, India

  • Worked on PCIE at subsystem and soc level verification of intel next generation processors šŸ’»šŸ’»
PCIESubsystem verificationSoC level verificationFunctional VerificationSystem on a Chip (SoC)

Education

Birla Institute of Technology and Science, Pilani

Electronics

Jawaharlal Nehru Technological University Kakinada (JNTUK)

Electrical ā€” Electronics and Communications Engineering

New York Institute of Technology

Computer Engineering

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