Suresh Abraboina

Product Engineer

Hyderabad, Telangana, India1 yr 10 mos experience

Key Highlights

  • 1.10 years of experience in Analog Layout Engineering
  • Hands-on experience with advanced technologies like TSMC N2-GAAFET
  • Proficient in Cadence Virtuoso for analog layout design
Stackforce AI infers this person is a skilled Analog Layout Engineer with expertise in semiconductor design.

Contact

LinkedIn

Skills

Core Skills

Analog Layout

Other Skills

Cadence VirtuosoCadence Virtuoso Layout EditorLvsLinuxDrcLayout Versus Schematic (LVS)Design Rule Checking (DRC)Physical VerificationLatch UPAntenna effects

About

1.10 year experience as Analog layout Engineer Hands on experience Analog layout design using cadence virtuoso XL on TSMC N2-GAAFET & TSMCN-N16,N7 FINFET , 28NM PLANAR Running DRC/LVS ,ERC ,Verifications Antenna checks in the layout. Basic knowledge of SKILL language in cadence Virtuoso Good knowledge of analog Layout concepts ( Antenna effect ,Latch up ,Crosstalk , Fingers & Multipliers WPE , MOSFET, CMOS fundamentals & fabrications process ).

Experience

1 yr 10 mos
Total Experience
1 yr
Average Tenure
10 mos
Current Experience

Amd

Layout Engineer (contract)

Jul 2025 – Present · 10 mos · Hyderabad, Telangana, India · On-site

  • working on high speed layout. TSMC N2 ( GAAFET).
Cadence VirtuosoAnalog Layout

Aiml services pvt ltd

Analog layout engineer

Jun 2024 – Jun 2025 · 1 yr · Hyderabad, Telangana, India · On-site

Cadence Virtuoso Layout EditorCadence VirtuosoAnalog Layout

Sumedhait

Analog Layout engineer

Aug 2023 – Mar 2024 · 7 mos · Hyderabad, Telangana, India

Cadence VirtuosoLvsAnalog Layout

Education

Holy Mary Institute of Technology and Science

Bachelor of Technology

Aug 2020 – Aug 2023

Samskruti College of Engineering & Technology

Diploma of Education

Jun 2017 – Mar 2020

Serenity model high school

SSC

Jun 2016 – Mar 2017

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