Prasad Ch

Software Engineer

Bengaluru, Karnataka, India9 yrs 8 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Experienced in ASIC design and layout engineering.
  • Proficient in multiple technology nodes including 90nm and 28nm.
  • Strong background in SRAM and analog layout design.
Stackforce AI infers this person is a Semiconductor Layout Engineer with expertise in ASIC design.

Contact

LinkedIn

Skills

Core Skills

LayoutIc

Other Skills

Standard cells layout designAnalog Layout designSRAM Layout designRoutingLVSDRC

Experience

9 yrs 8 mos
Total Experience
5 yrs 9 mos
Average Tenure
9 yrs 2 mos
Current Experience

Openfive

Senior ASIC Design Engineer

Aug 2018 – Present · 7 yrs 8 mos · Bengaluru, Karnataka, India

Intel corporation

Physical Design Engineer

Feb 2017 – Present · 9 yrs 2 mos · Bengaluru, Karnataka, India

Rv-vlsi design center

Layout Design Engineer

Oct 2015 – Apr 2016 · 6 mos · Bengaluru, Karnataka, India

  • Standard cells layout design in 90nm and 28nm technology nodes.
  • Analog Layout design in 180nm technology node.
  • SRAM Layout design from leaf cells in 28nm technology node.
LayoutStandard cells layout designAnalog Layout designSRAM Layout designIC

Education

Jawaharlal Nehru Technological University, Kakinada

Bachelor of Technology (B.Tech)

Jan 2011 – Jan 2015

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