Nov 2019 – Sep 2023 · 3 yrs 10 mos

• SoC Design and Integration Lead
• Manage a Design Team working on SoC/IP/DFD integration.
• Subsystem Architect of Low-Speed-Peripherals and USB sub-systems.
• uArch and System Verilog RTL coding of IP.

May 2017 – Oct 2019 · 2 yrs 5 mos

• Responsible for design and integration of various debug components at SoC level. This involves interacting with architect to understand debug features, interact with backend for creation of various floorplan aware topologies and integrating them with standard integration flow and checks.
• Ensuring quality through various SoC quality checks, CDC, LINT, constraints, exception, power-domain, and timing checks.
• Ensuring timing closure by placement refinements, repeater addition on debug topologies.

Apr 2014 – Apr 2017 · 3 yrs

• Design and verification owner for DFX component named MISR and feature named SBFT in Graphics product families.
• RTL coding using system Verilog and verification through checkers and BFMs.
• Automation through perl scripting to support verification env and generation of right collaterals.

Nov 2005 – Apr 2014 · 8 yrs 5 mos

• Backend methodology owner: Responsible for evolving, deploying, and tracking convergence to backend flows and quality checkers.
• Pioneered various low-power and power-domain checks for the very first MPP design in the absence of upf based implementation.
• Pioneered tcl based automation around fixing various DRC failures by innovative techniques ensuring high yield quality product.
• Owned various other sets of quality checks around STA constraints, clock-skew tracking, DFT compliance and certain generic quality checkers like Logic On Clock-Path, reset-path etc.
• Responsible for taking a block through the backend flow from floor-planning, synthesis, place-and-route, CTS, route-opt, timing and quality closures to GDS delivery.

May 2004 – Oct 2005 · 1 yr 5 mos · Bengaluru, Karnataka, India

• Responsible for adding Design-for-Testability (DFT) features like scan-chains and SPBIST and generating coverage reports on synthesized netlist.

Jan 2002 – Apr 2004 · 2 yrs 3 mos · Noida, Uttar Pradesh, India

• Worked on end-to-end backend flow for u-controller products. Starting from floor-planning, synthesis, CTS, PNR and Timing Closure and even a glimpse of packaging. Developed and deployed scan-insertion flow.