Deepak Kumar Singh — Software Engineer
VLSI Domain Skills SoC and IP level Verification. TB Methodology: OVM, UVM HVL: System Verilog Verification Methodologies: Coverage Driven Verification HDLs: Verilog and VHDL EDA Tool: Xilinx ISE,Modelsim & Questa,VCS,Verdi. Domain: ASIC/FPGA Design Flow, Digital Design & Verification methodologies Knowledge: RTL Coding, FSM based design, Simulation, Code Coverage, FunctionalCoverage, Synthesis,Static Timing Analysis Scripting Language: Perl ,shell(makefile)
Stackforce AI infers this person is a VLSI and ASIC design expert with a focus on digital verification methodologies.
Location: Bengaluru, Karnataka, India
Experience: 11 yrs 11 mos
Skills
- Vlsi
- Digital Design & Verification
Career Highlights
- Expert in VLSI domain with extensive verification skills.
- Proficient in multiple verification methodologies including OVM and UVM.
- Strong background in ASIC and FPGA design flows.
Work Experience
AMD
MTS Silicon Design Engineer (3 yrs 10 mos)
Qualcomm
Senior Engineer (4 yrs 1 mo)
Intel Corporation
Verification Engineer (client) (6 mos)
Qualcomm
Engineer II (client) (8 mos)
CISMA consultants Pvt Ltd (A wholly owned subsidiary of Verikwest Systems Inc, USA)
Design Verification Engineer (1 yr 6 mos)
Jenesys Technologies
System Engineer (1 yr)
Safran Engineering Services
Software Engineer (1 yr 3 mos)
Broadcom
Trainee Engineer (3 mos)
Education
B.TECH at imps college of engineering and technology (West Bengal university of technology)
12th at sunrise (english medium)school
10th at sunrise (english medium)schoolEditRe-order
