Dec 2019 – Nov 2021 · 1 yr 11 mos · Austin, Texas, United States

• RTL design engineer focusing on memory subsystem for high-performance CPU

Jun 2015 – Dec 2019 · 4 yrs 6 mos · Austin

• micro-architect load/store unit and branch unit, for high speed CPU cores

Mar 2013 – May 2015 · 2 yrs 2 mos · Austin, Texas Area

• Performance Modelling and Architecture Evaluation of DSP Core

Jul 2012 – Mar 2013 · 8 mos · Austin, Texas Area

• SOC verification Engineer
• Fusion System Architecture Verification
• Soc Infra Development

Aug 2010 – Jun 2012 · 1 yr 10 mos · Austin, Texas Area

• SOC Verification Engineer

Apr 2007 – Jul 2008 · 1 yr 3 mos

• Job Description: It involved research, designing, evaluating and implementing various IP’s for post processing block of video processor
• Compared various architecture implementation of 128 point FFT to obtain minimum area with given cycle constraint. It required implementation in verilog for better area estimate.
• Dealt with precision issue associated with fixed point FFT. Design and Implemented a low cost scheme that provided 16-20 times improvement in precision over existing FFT architecture.
• Designed low cost spatial and temporal filter to remove Gaussian noise from video. It involved implementing various algorithms in C and verilog.
• Performance Evaluation and stand alone verification for FFT and Gaussian Noise Reduction block

Jul 2006 – Apr 2007 · 9 mos

• Job Description: Verification engineer for SOC design for mobile application
• Stand Alone and System Level Verification of Flash Interface Unit which is a DMA engine to 8 Nand Memory and 1 Nor Memory
• Verified BCH and RS codes which were part of DMA engine. The test bench can be used for any BCH and RS code over Galois Field.