May 2022 – Dec 2022 · 7 mos · Remote

• Built methodologies and workflows to improve energy models using ML/statistical techniques to bridge the gap in power estimates between architecture development and final silicon implementation.
• Built a prototype for extracting ML model-based qualitative energy/power estimates from an emulation trace run using Palladium's Streaming Waveform feature, reducing the power estimation turnaround from 3 weeks to 4 hours.

Dec 2017 – Jul 2021 · 3 yrs 7 mos · Bengaluru Area, India

• Responsible for design verification of several hardware modules in Fungible's Data Processing Units (DPUs):
• (1) Crypto accelerators for ChaCha20-Poly1305, AES, SHA,
• (2) Fungible Node Controller, that sends/receives aggregated PCIe TLP messages over Ethernet
• (3) Regex Control (Regular Expression Search) hardware accelerator
• (4) ARM messaging hub that implements message translation between AXI transactions of ARM core and Fungible's chip-wide messaging protocol. Implements other functions like system counter and wakeup/watchdog timers.

Sep 2014 – Nov 2017 · 3 yrs 2 mos

• Designed and delivered these designs bug free:
• (1) Chip to chip link: An IO module that takes care of link layer. It handles link locking, error detection, data procurement and spraying onto all links, among others.
• (2) IO wrapper: which does integration of serdes and two types of link layer management blocks. It contains glue for handling two different proprietary protocols.
• (3) Memory crossbar: Memory module that handles 'N' independent writes and reads every cycle. Needs design optimizations for meeting timing,
• Work involves creating micro architecture, RTL implementation, logic synthesis and timing analysis.
• Worked on emulator to validate chip design.

Jul 2011 – Aug 2014 · 3 yrs 1 mo

• Performed verification at module and full-chip level for two networking chips that provide over- subscription management and packet processing with queueing and buffering, respectively.
• Individually owned the verification of
• (i) DDRIF - a module that provides external DRAM access for the entire chip
• (ii) RamBist: a bist engine module which checks an external Hybrid Memory Cube memory and
• (iii) Grant Table: a datapath grant processing module.
• (iv) FreeBit resource manager: which manages memory access by allocating and deallocating pointers to memory spaces.
• Work involves test planning, test bench creation, test-writing, running code coverage and gate level simulations among others.
• Worked extensively with both SystemC and UVM, using various tools from Cadence and Synopsis.

May 2010 – Jul 2010 · 2 mos · Pune/Pimpri-Chinchwad Area

• Worked on a project “Building Rich Person Profile for Context Services” which en- riches corporate user’s communication experience by gathering information about non- enterprise contact person and linking it to enterprise context.
• Devised an algorithm from scratch to extract information like name, affiliation, contact numbers, address, email-id and website URL from the signature part of the email.
• Using the database of information extracted from signatures of the user’s emails and online databases like Linkedin.com, Whitepages.com, a rich profile of the caller is generated and presented to the user.
• Realized by coding in Python and using various APIs for online databases and Natural Language ToolKit for extracting information from signatures in emails.
• It creates a rich context for the user and enhances his productivity.