R

Ravi Shankar Prasad

Director of Engineering

United States20 yrs 9 mos experience
Highly Stable

Key Highlights

  • Led multiple R&D projects in semiconductor industry.
  • Expert in SystemVerilog and low power technology.
  • Proven track record in team leadership and project management.
Stackforce AI infers this person is a Semiconductor R&D expert with extensive experience in SystemVerilog and low power technologies.

Contact

Skills

Core Skills

R&dLow Power TechnologyFault SimulationSystemverilogCode Coverage

Other Skills

DebuggingCo-simulationRegression TestingPythonVCSProject ManagementQuality AssuranceParser DevelopmentC++VerilogAlgorithms

Experience

20 yrs 9 mos
Total Experience
20 yrs 9 mos
Average Tenure
20 yrs 9 mos
Current Experience

Synopsys inc

10 roles

R&D Director

Promoted

Sep 2021Present · 4 yrs 8 mos

R&DDebugging

Sr Mgr, R&D

Promoted

Jun 2017Sep 2021 · 4 yrs 3 mos

  • Low Power Technology in VCS(Team size(geographically distributed)=20+): Working with a team of highly motivated and innovative engineers who are low power industry experts and fueling the Low Power innovation in VCS, and making the Low Power solution in VCS the best in the industry.
  • VC ZOIX(Team size(geographically distributed)=8+): Started work in fault simulation, started with cosimulation, later moved to full native simulation. Lead the product development, worked with experts, senior team members and other stake holders to define UI, semantics, and eco system for the product, gathered tasks, prioritized them, and worked towards their delivery. Supervised different team members for support of EVCD flow, fault injection with SFF, integration with FDB/FCC/FCM. Worked with stakeholders to educate them about usage. Setup different types of regressions for validations which harnessed existing functional simulation regressions. For fault simulation, biggest challenge was validating the correctness of different concurrent simulations, so, I implemented script in python which worked with VC ZOIX to validate different concurrent simulations on grid, which gave enough confidence to team of the quality of the tool, and helped them move faster without breaking existing functionality. Uniqueness of the methodology was that it didn't require writing any new testcase; it could harness existing functional simulation regression for all the validation. Using this methodology, we could validate simulations which if run on single machine serially would have taken months and years to validate.
  • SystemVerilog in VCS [Team(geographically distributed) size= 8+]: Continued leading geographically spread team, successfully groomed next level leaders, defining roadmap for component, finalizing, scoping, and timely delivery of multiple projects for quality, performance and enhancements.
Low Power TechnologyFault SimulationCo-simulationSystemVerilogRegression TestingPython

R&D Engineer, Sr Staff

Jan 2017Jun 2017 · 5 mos

Mgr II, R&D

Jun 2016Jan 2017 · 7 mos

  • SystemVerilog in VCS [Team(geographically distributed) size= 7+]: Took complete ownership of SV component in VCS. Worked with all the stakeholders on deciding roadmap of the component, worked with team members for delivering on quality goal, defined projects for releases, worked with architect and technical experts for scoping out projects, and then supervised team members for implementation of the projects. Architected multiple performance projects[optimization related to event handling, assignment of arrays, task/function call improvement] and worked with team members for implementation.
SystemVerilogProject Management

Mgr II, R&D

Promoted

Aug 2013Jun 2016 · 2 yrs 10 mos

  • SystemVerilog in VCS- Took up the quality ownership of component and drove all the quality efforts for the component for release and patches. Continued supporting customer in debugging designs, fixing issues, and providing enhancements. Worked on optimization of $cast support. Architected and supervised team(team size=4) for multiple optimizations, quality items(class static member propagation...) , and customer enhancements(finalize support, strings on ports, foreach for multidimensional array..).
SystemVerilogQuality Assurance

R&D Engineer, Staff

Jun 2013Aug 2013 · 2 mos

R&D Engineer, Sr II

May 2010Jun 2013 · 3 yrs 1 mo

  • SystemVerilog in VCS - architected and supervised semantics correction of wait/disable fork. optimized handing of fork-join_none construct, implemented return optimization for stack unrolling, optimized disable support, added support for interface class in SV. Worked with my team(size=3) for multiple optimization, quality(%p support and streaming operator) and enhancements.
SystemVerilog

R&D Engineer, Sr I

Promoted

Nov 2007May 2010 · 2 yrs 6 mos

  • SystemVerilog in VCS - Added support for NBA trigger and dynamic events, architected and supervised wait_order support, worked in random stability and Fine Grain Process Control, dabbled in Garbage collector, functional coverage and NTB, supported inheritance for semaphore and mailbox.
SystemVerilog

R & D Engineer - II

May 2006Nov 2007 · 1 yr 6 mos

  • Worked on code coverage constant filtering in VCS- enhanced feature for input file support which could handle complex expression by writing a small yacc/lex based parser for the file input file.

R & D Engineer - I

Jun 2005May 2006 · 11 mos

  • Worked on code coverage constant filtering in VCS- revamped the entire handling which improved constant filtering performance dramatically for multiple customer designs.
  • Worked on Pioneer-NTB TB(Testbench) simulator- fixed bugs, implemented enhancements.
Code CoverageParser Development

Education

Indian Institute of Technology, Kanpur

BTech — Electrical/Electronics

Jan 2001Jan 2005

Indian Institute of Technology, Kanpur

Bachelor of Technology - BTech

Jan 2001Jan 2005

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