Mar 2023 – Aug 2024 · 1 yr 5 mos · Austin, Texas Metropolitan Area · Hybrid

• DSP's play a pivotal role in Qualcomm's SoC ecosystem for media processing, modems, and neural processing units (NPU). I specialize in developing architecture and micro-architecture models in C++ focused on studying performance, power, and area trade-offs for DSP's diverse roles. My responsibilities include extracting architectural innovations from workload analysis, conducting limit studies to shape the product roadmap, designing advanced profiling tools for DSP, and conducting performance validation processes.

Jun 2020 – Aug 2020 · 2 mos · Menlo Park, California, United States

• Built a tool to dynamically identify candidate functions for optimization consuming most CPU cycles at Facebook software infrastructure. Ensured quality code delivery by refining requirements, strategic algorithm design based on graph theory, modular code development, testing with real-time data & visualizing contextual information. Took initiative to collaborate and integrate the tool into two established internal products of the site efficiency team.

Jul 2019 – Dec 2022 · 3 yrs 5 mos

Jun 2018 – Dec 2022 · 4 yrs 6 mos

• Store Reuse Time Predictor: Designed hardware prediction modules that selectively perform low retention writes using store reuse time to address endurance and energy concerns for Resistive RAM-based main memory. Demonstrated an increase in the average lifetime by 6.4×, outperforming the state-of-the-art by 302% while cutting memory energy consumption by 2.12×, derived from extensive simulation-based evaluation.
• Monolithic 3D processors: Analyzed physical design trade-offs in 3D integration of Resistive RAM based main memory into processor die. Designed an accelerator architecture to match the massive amount of fine-grained parallelism afforded by this memory system. Developed a cycle-accurate simulator in C++ to compare performance against HBM2.

Aug 2016 – May 2018 · 1 yr 9 mos

• Teaching and lab design: Computer Organization, Digital Computer Design and Operating Systems.

Nov 2014 – Aug 2016 · 1 yr 9 mos

• ASIC Verification IP Development in UVM
• I acquired in-depth knowledge of NAND flash memory and its controllers working as a Hardware Engineer in Memory Solutions. I also gained expertise in System on Chip verification methodology UVM and SystemVerilog. My project entailed verification of NVMe based controller used in flagship Samsung SSD solutions for enterprises attached to the host side through PCIe bus. Here I learnt to design a plug and play verification IP to drive random as well as directed stimulus to the SoC RTL.

Jun 2014 – Nov 2014 · 5 mos

• I was part of Security Solutions team where I worked on state of the art image and signal processing techniques. This included work on abandoned object detection for surveillance cameras, image processing techniques for the smartphone gallery software and digital image noise removal techniques for Samsung’s smartphone camera software.

May 2013 – Jul 2013 · 2 mos · Bangalore, India

• Developed a tool to measure round trip performance metrics of IP network between two host devices.
• Implementation was based upon the specifications given in RFC (Request for comments) 5357 & RFC 4656.
• Unique feature was flexibility to choose sessions on various TCP/IP suite protocols viz. TCP, UDP & SCTP
• Tested and demonstrated the utility as a menu driven program, indicating network performance by minimum-maximum-average latency, packet loss and jitter.

May 2012 – Jul 2012 · 2 mos · Mumbai Area, India

• Assisted in development of a wireless system to monitor and circulate status of various entities in an assembly.
• Used Xbee modules to send and save data in an SD card, to be examined afterwards for contingency analysis.