Aniruddha Gupta — CEO
Aniruddha Gupta is currently working as Sr. System Architect for grace hopper super chip in NVIDIA. In this role, he is actively defining power and boot architecture. He is also evaluating the current architecture from power/performance optimization at architectural level. Previously in NXP: He worked as SoC Architect, Power Management Architect ,SoC Frontend designer and Power Management Controller (PMC) IP RTL designer for various automotive devices. He also Co-authored 8 international level publications and has 2 patent grants in power management . He was invited thrice for presenting his work in the Low Power Design conference in NXP Headquarter at Eindhoven, Netherlands. As SoC Architect: He was responsible for defining chip level clocking, reset , power management. He also has a good knowledge of Automotive Safety, Security and Boot architecture. He is also well versed with using Technical requirement management system (DOORs) used for meeting ISO26262 in automotive. As SoC Frontend Designer: He was primarily involved as: 1. Clock, reset , power management ,security and safety related IP integrator. Along with integration, he supported verification and Backend teams for any design fixes in this domain. 2. Expert reviewer of customer reference manual , verification and validation plan for above mentioned domains.. 3. Interface with systems team to approve and support design feasibility of project. 4. Cross functional expert for providing design inputs on synthesis constraints, timing constraints, power constraints and verification constraints. 5. Low power expert to define Architecture and RTL level power reduction techniques. 6. SoC CDC/RDC/Lint Signoff expert in multiple projects. He also worked on enhancing methodology for these signoff . 7. Silicon support and root cause expert, where he was supporting many taped out projects and had root caused many critical customer issues. He also worked on driving root cause analysis methodology within SoC FE team to ensure higher quality in future projects..
Stackforce AI infers this person is a Semiconductor Architect with expertise in power management and SoC design.
Location: Bengaluru, Karnataka, India
Experience: 15 yrs 6 mos
Skills
- Power Management
- Boot Architecture
- Reset Architecture
- Leadership
- Rtl Coding
Career Highlights
- Co-authored 8 international publications in power management.
- Holds 2 patents in power management.
- Presented at Low Power Design conference thrice.
Work Experience
Iontra Inc
Principal IC Architect (2 yrs 5 mos)
NVIDIA
Senior System Architect (2 yrs 4 mos)
NXP Semiconductors
Principal Design Engineer (11 mos)
Staff Design Engineer (3 yrs 3 mos)
Lead Design Engineer (1 yr 8 mos)
Senior Design Engineer (2 yrs 5 mos)
Design Engineer (2 yrs 5 mos)
CDOT
Trainee (2 mos)
Siemens
Trainee (1 mo)
plc- institute of electronics
trainee (0 mo)
Education
Master’s Degree at Indian Institute of Technology, Delhi
B.Tech at National Institute of Technology Kurukshetra
12th at Greenfield public school (C.B.S.E affiliated)
10th at Gita Niketan Sr. Sec. Public School