Aniruddha Gupta

CEO

Bengaluru, Karnataka, India15 yrs 6 mos experience
Highly Stable

Key Highlights

  • Co-authored 8 international publications in power management.
  • Holds 2 patents in power management.
  • Presented at Low Power Design conference thrice.
Stackforce AI infers this person is a Semiconductor Architect with expertise in power management and SoC design.

Contact

Skills

Core Skills

Power ManagementBoot ArchitectureReset ArchitectureLeadershipRtl Coding

Other Skills

AMBA AHBARMARM ArchitectureASICApplication-Specific Integrated Circuits (ASIC)CC++CDCClockingDebuggingDesign EngineeringEmbedded SystemsFPGAField-Programmable Gate Arrays (FPGA)HAL

About

Aniruddha Gupta is currently working as Sr. System Architect for grace hopper super chip in NVIDIA. In this role, he is actively defining power and boot architecture. He is also evaluating the current architecture from power/performance optimization at architectural level. Previously in NXP: He worked as SoC Architect, Power Management Architect ,SoC Frontend designer and Power Management Controller (PMC) IP RTL designer for various automotive devices. He also Co-authored 8 international level publications and has 2 patent grants in power management . He was invited thrice for presenting his work in the Low Power Design conference in NXP Headquarter at Eindhoven, Netherlands. As SoC Architect: He was responsible for defining chip level clocking, reset , power management. He also has a good knowledge of Automotive Safety, Security and Boot architecture. He is also well versed with using Technical requirement management system (DOORs) used for meeting ISO26262 in automotive. As SoC Frontend Designer: He was primarily involved as: 1. Clock, reset , power management ,security and safety related IP integrator. Along with integration, he supported verification and Backend teams for any design fixes in this domain. 2. Expert reviewer of customer reference manual , verification and validation plan for above mentioned domains.. 3. Interface with systems team to approve and support design feasibility of project. 4. Cross functional expert for providing design inputs on synthesis constraints, timing constraints, power constraints and verification constraints. 5. Low power expert to define Architecture and RTL level power reduction techniques. 6. SoC CDC/RDC/Lint Signoff expert in multiple projects. He also worked on enhancing methodology for these signoff . 7. Silicon support and root cause expert, where he was supporting many taped out projects and had root caused many critical customer issues. He also worked on driving root cause analysis methodology within SoC FE team to ensure higher quality in future projects..

Experience

Iontra inc

Principal IC Architect

Oct 2023Present · 2 yrs 5 mos · Bengaluru, Karnataka, India · Hybrid

Nvidia

Senior System Architect

Jun 2021Oct 2023 · 2 yrs 4 mos · Bengaluru, Karnataka, India · Hybrid

  • He worked on grace hopper superchip and defined power and boot architecture specification. He also evaluated the architecture for power/performance optimization at architectural level.
boot architecturePower Managementreset architectureSemiconductor EngineeringtensilicaC+++3

Nxp semiconductors

5 roles

Principal Design Engineer

Jul 2020Jun 2021 · 11 mos

  • Worked as SoC Architect on different products in automotive radar family. Also guiding team on clocking ,reset , power management and safety architecture
Power Managementreset architectureSemiconductor EngineeringVerilogTeamworkLow-power Design+3

Staff Design Engineer

Apr 2017Jul 2020 · 3 yrs 3 mos

  • Worked in SoC Arch & FE Integration Design team as SoC Architect for automotive radar products
Power Managementreset architectureSemiconductor EngineeringVerilogLow-power DesignVery-Large-Scale Integration (VLSI)+2

Lead Design Engineer

Jul 2015Mar 2017 · 1 yr 8 mos

  • Worked as Power management architect ,low power expert and PMC RTL designer for almost all products happening in Noida Automotive Center.
Power Managementreset architectureSemiconductor EngineeringCDCVerilogLow-power Design+5

Senior Design Engineer

Promoted

Jan 2013Jun 2015 · 2 yrs 5 mos

  • Worked as frontend integration engineer for Body and gateway family of products in automotive
Power Managementreset architectureSemiconductor EngineeringCDCVHDLVerilog+6

Design Engineer

Jul 2010Dec 2012 · 2 yrs 5 mos

  • Worked as frontend integration engineer for general market products and automotive products
RTL CodingSemiconductor EngineeringCDCVHDLVerilogVery-Large-Scale Integration (VLSI)+2

Cdot

Trainee

Jun 2009Aug 2009 · 2 mos

  • I worked in GPON Hardware division. Under guidance of Mr. Praveen Kumar ( Team leader GPON), I studied and observed GPON system and Designed CRC-8 used in transmission of ATM cells using VHDL.
C++

Siemens

Trainee

Jun 2008Jul 2008 · 1 mo

  • Here i worked in Automation & drives division and i observed Siemens S7 PLC.
C++

Plc- institute of electronics

trainee

Jan 2008Jan 2008 · 0 mo

  • learnt 8051 and basic electronics hands-on training.

Education

Indian Institute of Technology, Delhi

Master’s Degree — VLSI

Jan 2015Jan 2018

National Institute of Technology Kurukshetra

B.Tech — Electronics & Communication

Jan 2006Jan 2010

Greenfield public school (C.B.S.E affiliated)

12th — Non-medical

Jan 2005Jan 2006

Gita Niketan Sr. Sec. Public School

10th

Jan 2003Jan 2004

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