Ganesan Nagasubramanian

CTO

Bangalore, Karnataka, India31 yrs experience

Key Highlights

  • Over 30 years of expertise in semiconductor engineering.
  • Proven track record in improving efficiencies and reducing costs.
  • Strong leadership in managing high-performance technical teams.
Stackforce AI infers this person is a Semiconductor Engineering expert with extensive leadership experience in product development and implementation.

Contact

Skills

Other Skills

Product DevelopmentEntrepreneurshipR&DASICSoCVLSIStart-upsStrategySemiconductorsTiming ClosureManagementLeadershipMicroprocessorsICRTL design

About

Professional Profile: • Performance-driven, entrepreneurial engineering professional with over 30 years of expertise in Product Implementation, Methodology development, Business Unit Development, R&D engineering • Proactive self-starter with track record of initiative, personal responsibility, ownership of work and reputation for making things happen. • Highly analytical thinker with demonstrated ability to scrutinize technical data. • Strong leader who effectively motivates teams and directs various level strategic initiatives. • Superlative interpersonal communicator, presenter, and negotiator. Delivered effective presentations to corporate senior executives. • Creative, dependable, and enthusiastic change agent with proven track record in improving efficiencies, reducing costs, and increasing revenues. • Skilled coalition-builder with multicultural experience through extensive Asian, North American, Middle East and European travel. • Passionate about Work and Ability to deal with Challenges. • Efficiently Collaborate with multi-site Cross Functional teams. Areas of Expertise: • CPU Sub System Design • Core IP, Platform Verification • Boot ROM Verification • Analog Mixed Signal System Resource Sub system • Advanced CPU Implementation strategy with Performance, Power, Area (PPA) know-how. • Semiconductor product development/implementation. • Successful start-up organization engagement. • Setup Implementation group at Business Unit level across sites. • R&D engineering. • RTL to GDSII. • High-performance, Low Power Synthesis. • Physical Design (PD) Implementation. • SoC, Module/Block level Floorplan and Implementation. • Place and Route (P&R). • Design Flow and Methodology Improvements. • Package design. • Design for Test (DFT). • Static Timing Analysis (STA). • Die size estimation and design planning. • High Speed Clock tree methodology and Implementation. • Signal Integrity and Reliability analysis. • Power Analysis and Estimation. • Power, Timing Sign-off Convergence and Optimization. • Low Power and High-Performance Design Implementation. • Physical Verification. • Formal Verification. • Program Management. • Resource’s planning, Scheduling. • High performance team management. • Mentoring, Coaching. • Project Management. • Bringing up Strong next level Technical and Managerial Leaders within the organisation. • First time Offshore Development Center (ODC) Setup. • Front-End Team Business Unit Responsibility and Ownership. • Ownership and Responsible for StarVLSI Training Institute (Finishing School).

Experience

31 yrs
Total Experience
2 yrs 11 mos
Average Tenure
1 yr 5 mos
Current Experience

Tata consultancy services

Head - Semiconductor Engineering

Dec 2024Present · 1 yr 5 mos · Bangalore Urban, Karnataka, India · On-site

  • Technical Leadership Role in building teams for delivering products in various market segments.

Leadsoc technologies pvt ltd

Vice President

Apr 2024Oct 2024 · 6 mos · Bangalore Urban, Karnataka, India · On-site

  • Technical Leadership Role in enabling first time Off-Shore Development Center (ODC) Implementation Specific (RTL to GDSII) Projects. Front-End Team Business Unit Ownership and Responsibility. Owned and Responsible for StarVLSI Training Institute (Finishing School).

Infineon technologies

Sr. Director

Jun 2022Jun 2023 · 1 yr · Bengaluru, Karnataka, India

  • Technical Leadership Role in IoT, Compute & Wireless (ICW) IP team at Infineon Technologies India Private Limited.
  • Owned and Responsible for CPU Sub system(CPUSS), System Resources Sub system(SRSS), Core IP, Core Platform and Boot ROM Verification.

Qualcomm

2 roles

Director Of Engineering

Promoted

Aug 2018Jun 2022 · 3 yrs 10 mos

  • Technical Leadership Role in Advanced CPU Implementation at Qualcomm India Private
  • Limited, Bangalore, India. Managed large size high performance technical teams across sites
  • to deliver flawless, First Time Right, Competitive CPU Sub Systems across product segments for the last 7+ Years. Responsible for CPU Performance, Power, Area and Thermal (PPAT) metrics.

Principal Engineer

May 2015Aug 2018 · 3 yrs 3 mos

  • Involved in SoC Product Implementation. Worked as SoC Design Manager for first Six months period. Taken up CPU Implementation Team Leadership Role as a next step. Responsible for CPU Performance, Power, Area and Thermal (PPAT) metrics. Managed large size CPU team at Qualcomm.

Amd

2 roles

Senior Manager

Jan 2013Jan 2015 · 2 yrs · Bangalore, India

  • Involved in Accelerated Performance Unit(APU) products development.

PMTS Design Engineer

Jan 2011Jan 2013 · 2 yrs · Bangalore, India

  • Involved in Accelerated Performance Unit(APU) products development.

Lantiq

Senior Manager

Jan 2003Jan 2011 · 8 yrs · Bangalore, India

  • Involved in Wireline Products development. Formerly part of Wireline Business Unit of Infineon Technologies.

Texas instruments

Technical Leader

Jan 2002Jan 2003 · 1 yr · Bangalore, India

  • Involved in Wireless platform based products development.

Catamaran-infineon technologies, san jose, ca, usa

Staff Engineer

Jan 2001Jan 2002 · 1 yr · San Jose, CA, USA

  • Formerly Known as Catamaran Communications, got acquired by Infineon Technologies.
  • Involved in development of World's First 40G Single Chip Framer-Mapper Device.

Philips semiconductors, san jose, ca, usa.

Design Engineer

Jan 1998Jan 2001 · 3 yrs · San Jose, CA, USA

  • Involved in High Definition TV, Set-top box application ASIC products development.

Technology rendezous inc, san jose, ca, usa.

VLSI Design Engineer

Jan 1996Jan 1998 · 2 yrs · San Jose, CA, USA

  • Involved in Firewire(IEEE1394) product development.

Arcus technology

VLSI Design Engineer

Jan 1994Jan 1996 · 2 yrs · Bangalore, India

  • Involved in Microcontroller ASIC product development.

Education

Indian Institute of Management Bangalore

EGMP — Executive General Management Programe

Jan 2009Jan 2010

Birla Institute of Technology and Science, Pilani

Master of Engineering — Microelectronics

Jan 1992Jan 1993

Alagappa University

Master of Science

Jan 1990Jan 1992

Madurai Kamaraj University

Bachelor of Science — Physics

Jan 1987Jan 1990

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