K

Karan Handa

Software Engineer

Bengaluru, Karnataka, India8 yrs 2 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 6.5 years of experience in digital design engineering.
  • Expertise in high-speed interfaces like PCIe and MIPI.
  • Strong background in power integrity and optimization.
Stackforce AI infers this person is a Digital Design Engineer specializing in high-speed interface technologies within the semiconductor industry.

Contact

Skills

Core Skills

Digital Ic DesignRtl Design

Other Skills

Synopsys SpyglassVERILOGUFI and NIP ProtocolPCIEJasper GoldVoltusScan insertionDFT/ATPGCommunicationVery-Large-Scale Integration (VLSI)System on a Chip (SoC)Application-Specific Integrated Circuits (ASIC)SemiconductorsElectronicsWireless Networking

About

Highly skilled Digital Design Engineer with over 6.5 years of hands-on experience in the design, development, and validation of complex digital systems, particularly in high-speed interfaces such as PCIe, MIPI, and SerDes. My expertise spans RTL design, front-end flows, and comprehensive verification using industry-standard protocols. Throughout my career, I have gained profound experience in implementing and optimizing design methodologies across various high-performance domains, from validating corner cases and enhancing IP quality performing thorough front-end static checks and achieving production-level validation. With a strong foundation in PCIe Gen6, MIPI, and high-speed SerDes PHY designs, I have successfully integrated advanced protocol knowledge and architecture to develop robust and compliant PHYs. My hands-on experience in using tools like Spyglass, Jasper Gold for CDC and Lint checks, as well as Scan insertion and pattern generation for DFT/ATPG, has equipped me to drive design validation at every stage of the development cycle. I am also well-versed in working with power integrity solutions like Voltus, where I have focused on optimizing both static and dynamic power at full-chip and cell levels to ensure high-efficiency designs. In addition, I bring advanced skills in working with various network tools, such as Wireshark, for testing and validating co-existence scenarios in WLAN/BT systems. I have developed a strong understanding of wireless communication protocols and co-existence testing, which has allowed me to evaluate throughput, interference, and interoperability in diverse conditions. My hands-on experience with ASIC design flows, low technology nodes and power gating methodologies have enhanced my ability to manage power efficiency in designs while ensuring compliance with industry standards. As I continue to contribute to innovative projects, I remain dedicated to delivering high-quality digital designs that meet the most demanding performance in today’s competitive technology landscape. Actively looking for opportunities, please feel free to reach out to me at khanda.jobs@gmail.com.

Experience

8 yrs 2 mos
Total Experience
1 yr 7 mos
Average Tenure
3 yrs 9 mos
Current Experience

Intel corporation

Design Engineer

Aug 2022Present · 3 yrs 9 mos · Bengaluru, Karnataka, India

  • As Digital Design Engineer, I worked on Universal Bridge IP for Gen4 under the SCF team, using in-house and standard protocols, as well as handled front-end static check tools using Synopsys Frontend Tools.
Digital IC DesignSynopsys SpyglassVERILOGUFI and NIP ProtocolRTL Design

Synopsys inc

Design Engineer

Nov 2021Aug 2022 · 9 mos · Hyderabad, Telangana, India

  • • Working in Digital Design team as a Frontend RTL Designer in RMMI - MPHY team using MIPI Protocol and handling frontend flows such as CDC, Lint, Synthesis for the project.

Cadence design systems

Design Engineer

Oct 2018Oct 2021 · 3 yrs · Bengaluru, Karnataka, India

  • ·        As part of the High Speed SerDes team in IP Group, I worked as a Design Engineer and on PCIE Gen6 PCS layer encoding and decoding blocks and handled front-end flow.
  • ·        Integrated PCIe protocol and pipe architecture knowledge to develop pipe-compliant PHY. Integrated the Pipe PHY DUT with VIP while testing on scenarios like data transfer, rate and power change, loopback, polarity inversion, and lane reversal, in accordance with the requirements.
  • ·        Using Jasper Gold tool performed CDC, Lint and worked on Scan insertion and pattern generation for DFT/ATPG using Modus to check the coverage
  • ·        Worked in Voltus IC Power Integrity Solution used for full-chip and cell-level power, IR sign-off. Being an Intern there, I was responsible for creating designs (using ASIC flow) on lower technology nodes involving scan flops, retention flops using clock gating and power gating methodologies and analysed Static and Dynamic power.

Cypress semiconductor corporation

System Validation Engineer

Jul 2018Oct 2018 · 3 mos · Bengaluru, Karnataka, India

Mediatek

Intern

Jun 2017Dec 2017 · 6 mos · Noida Area, India

Netmax technologies pvt ltd

TRAINEE

Jun 2016Jul 2016 · 1 mo · Chandigarh Area, India

E- yantra robotics initiative-indian institute of technology-bombay

Team Member

Oct 2015Mar 2016 · 5 mos · MUMBAI

Education

YMCA University of Science & Technology

Bachelor's degree — Electronics and Communications Engineering

Jan 2014Jan 2018

P.K.R Jain Sr. Sec. Public School ,Ambala City

Jan 2011Jan 2013

P.K.R Jain Sr. Sec. Public School ,Ambala City

Jan 2001Jan 2011

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