Shankar Prasad (Agrawal)

Product Engineer

Bengaluru, Karnataka, India9 yrs 8 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

9 years of experience in IP and Subsystem Micro-architecture.
Expertise in RTL design for high-complexity SoCs.
Proven track record of on-time delivery with high quality.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in RTL and Microarchitecture.

Contact

shankarprasad95@gmail.com LinkedIn

Skills

Core Skills

Rtl DevelopmentMicroarchitectureRtl CodingSystem Architecture

Other Skills

AXIAlgorithmsBusiness DevelopmentBusiness strategyCC++CadenceDDRDigital Circuit DesignDigital IC DesignEDAGPUIP CamerasISPImage

About

I have around 9 years of experience post MTech in IP and Subsystem Micro-arch definition, RTL implementation and all front end design activities. Experience in scratch design for both IP and subsystem with high complexity. Experience working at SoC level. RTL Design, IP Design and Micro-architecture definitions. IP development in field of Image processing for various products. Sub-system Design for GPU, Peripheral IPs in TPU/Pixel and Exonys Mobile SoCs SoC Design and execution for Samsung Exynos I have track record of on time delivery with best quality. Design Rule Check(CDC,SPY-DFT, SPY-Lint, DCLINT, SFR test) at IP, Sub-System and Chip level. UPF writing, Low Power Strategy and Checks. Defining sub-system level sequences and clock and power management hardware module. GLS Setup and Run at SoC level. SoC Environment and database management. Debug DV issues closely with DV team and help to increase test plans and coverage. STA, Timing fixes in RTL. Know about ISP, Coresight Debug, LPDDR, GPU, AMBA protocols and Interconnects. Domains: IP Design, Sub-system Design, SoC Design

Experience

Nxp semiconductors

2 roles

IP RTL Design

May 2025 – Present · 10 mos · On-site

ISP IP Micro-arch development and RTL implementation for Vision application of various SoCs of NXP like i.MX family and products targeted for automotive and Industrial applications.

RTL DevelopmentIP CamerasMicroarchitectureRTL Design

IP RTL Design

Jul 2024 – May 2025 · 10 mos · On-site

ISP IP Micro-arch development and RTL implementation for Vision application of various SoCs of NXP like i.MX family and products targeted for automotive and Industrial applications.

RTL DevelopmentIP CamerasMicroarchitectureRTL Design

Google

2 roles

RTL Design Engineer

Jun 2023 – Jul 2024 · 1 yr 1 mo

RTL Design for Multimedia IPs for Pixel SoCs
Camera CSIS and ISP Design.
Microarchitecture and RTL design for CSIS IP and it's component IPs after rigorous discussion with architecture and cross functional teams.
RTL Coding in System Verilog.

RTL CodingImagecameraISPMicroarchitectureSystemVerilog

ASIC Design Engineer

Jan 2022 – Jun 2023 · 1 yr 5 mos

GPU Subsystem
Define architecture and mircro-architecture features, write specifications and understand implementation tradeoffs (performance, power, frequency, etc,).
Define the GPU block level design document such as interface protocol, block diagrams, transaction level flow, control registers, pipelines etc.
Perform RTL development process (coding and debug in Verilog/SystemVerilog) function/performance simulation debug and Lint/CDC/FeV/PowerIntent checks.
Contribute to the SoC level integration. Participate in synthesis, timing/power closure and silicon bring-up.
Participate in test plan and coverage analysis of the block and SOC-level verification.

RTL CodingSystem ArchitectureGPUProblem SolvingRTL DevelopmentAXI

Samsung electronics

3 roles

Staff Engineer

Mar 2021 – Jan 2022 · 10 mos

Problem SolvingRTL DevelopmentAXI

Associate Staff Engineer

Mar 2019 – Feb 2021 · 1 yr 11 mos

DDRRTL CodingProblem SolvingAXI

Senior Engineer

Sep 2018 – Feb 2019 · 5 mos

Problem SolvingRTL DevelopmentAXI

Marvell semiconductor

Digital IC Design Engineer

Jul 2017 – Sep 2018 · 1 yr 2 mos · Pune Area, India

RTL coding and required changes in existing wireless IPs based on IEEE802.11ax standard.
CDC Set-up (Spyglass) and Checks at chip level and IP level of Wireless SoC.
DFT/Lint Set-up (Spyglass) and Checks at chip level and IP level of Wireless SoC.
SoC Integration.

RTL CodingProblem SolvingRTL DevelopmentAXI

Iit bombay

2 roles

Teaching Assistant for System Design ( Post Graduate Course)

Jan 2017 – May 2017 · 4 mos

RTL CodingProblem SolvingRTL DevelopmentAXI

Teaching Assistant for Microelectronics Simulation Lab ( Post Graduate Course)

Jul 2016 – Dec 2016 · 5 mos

Indian institute of technology, bombay

Teaching Assistant for Digital system Design (Undergraduate Course)

Jan 2016 – May 2016 · 4 mos

Iit indore

Junior Research Fellow

May 2015 – Jul 2015 · 2 mos · Indore Area, India

New device structure to increase retention time, low power consumption, endurance, fast writing of capacitorless 1T DRAM (Z-DRAM) for short channel length. Have simulated various way for store data in transistor and their comparison in term of power consumption and writing speed.

Paramount communications ltd

Intern at position of Analyst Engineer

May 2014 – Jul 2014 · 2 mos · New Delhi Area, India

The project aims to understand Railway technology system followed worldwide, and study of measures to be taken in order to promote safety against fire in the Indian Railways. It also emphasizes on the recommended material to be used for making the Railway coaches safer. After a detailed analysis of the present scenario of Indian Railways, it is strongly suggested that Fire alarm detection and suppression system may be installed.