Vidya Naidu — Software Engineer
Experienced RTL Engineer with 5+ years of experience in ASIC design flow, encompassing micro-architecture development, RTL design, synthesis, linting, CDC/RDC analysis, and timing closure. Proficient in RTL coding, Spyglass, and formal verification using Jasper Gold. Demonstrated ability to deliver high-quality IP designs across advanced technology nodes like 3nm and 5nm, collaborating with cross-functional teams to ensure seamless integration and performance optimization. Hands-on experience in frontend ownership across ASIC design flow for IP development.
Stackforce AI infers this person is a highly skilled ASIC design engineer with expertise in advanced technology nodes.
Location: Telangana, India
Experience: 9 yrs
Career Highlights
- 5+ years of experience in ASIC design flow.
- Expertise in RTL design and timing closure.
- Proficient in formal verification and collaboration.
Work Experience
AMD
Member of Technical Staff (1 yr)
NVIDIA
Senior ASIC Design Engineer (4 yrs 9 mos)
ASIC Design Engineer (2 yrs 1 mo)
Microsemi Corporation
Design Verification Engineer (5 mos)
Intern (9 mos)
Education
MS by Research at International Institute of Information Technology Hyderabad (IIITH)
Bachelor of Engineering - BE at Bhilai Institute of Technology (BIT), Durg
HSSC at Delhi Public School - India
