Sri Harsha Munagala

Product Manager

Bengaluru, Karnataka, India6 yrs 8 mos experience

Highly StableAI Enabled

Key Highlights

Expert in SoC Power Management and Low-Power Design
Led end-to-end chipset cycle for major mobile projects
Awarded multiple recognitions for outstanding performance

Stackforce AI infers this person is a Silicon Architect specializing in Low-Power SoC design for mobile technologies.

Contact

Skills

Core Skills

Soc Power ManagementComputer Architecture

Other Skills

System on a Chip (SoC)Microsoft OfficeLow Power SystemsDDR SDRAMAnalytical SkillsCommunicationArtificial Intelligence (AI)LeadershipSystems AnalysisC (Programming Language)Microsoft ExcelMicrosoft PowerPoint

About

○ Silicon Architect with expertise in Micro-Processor Architecture and SoC Power Management. ○ Responsible for developing industry leading Low-Power design by maintaining a constant focus on Power Consumption in our ASIC, System Software and Reference Designs, listening to our customers and analyzing the competition. ○ Experienced in Chipset / SoC Level use case power projection and correlation. ○ Managed End to End chipset cycle from Pre-Sil to Post-Sil in multiple projects in Mobile Segment for Qualcomm and Google.

Experience

6 yrs 8 mos

Total Experience

4 yrs 9 mos

Average Tenure

1 yr 11 mos

Current Experience

Google

ASIC Power Engineer

May 2024 – Present · 1 yr 11 mos · Bengaluru, Karnataka, India · Hybrid

Awarded 3xPeer bonus and 4xSpot Bonus
Memory Silicon Architect, responsible for the end-to-end power design process, including power budgeting at concept phase, development of SoC power modeling tool using Python to project system level use case power post project inception and correlation of memory path components power in post-silicon.
Define test cases (PtPx vector) for pre-silicon and post-silicon power validation, analysis and improve accuracy of power model.
Analyze and monitor power estimates from PtPx vector throughout the SoC design process to achieve the power goals.
Collaborate with architecture, Design and Implementation teams to evaluate and optimize power management architecture of SoC with specific focus on Memory Path Components.

SoC Power ManagementComputer Architecture

Qualcomm

3 roles

Senior System Engineer

Dec 2022 – Apr 2024 · 1 yr 4 mos

Chipset Power Lead for 7 Gen 3, Next Gen 8 Series Qualcomm Mobile Segment Project
Received Orion Award
Working on SoC Infra Power improvement on major IPs including CPU, GPU, Modem, ISP and Memory controller.
Coming up with Optimizations, tuning and commercialization leading to improve battery life from SW and HW perspective.
SoC Power Grid Design/ Optimization
Platform level use case power modeling for Mobile technology areas: Modem (3G/4G/5G), Multimedia, Connectivity and days of use composite power suite.

SoC Power ManagementComputer Architecture

System Engineer

Promoted

Dec 2020 – Dec 2022 · 2 yrs

Chipset Power Lead for Qualcomm Snapdragon Mobile Processors : SM6115, SM6225, 7 Gen 1.
Received Impact Award and Orion Award.
Developed tools and scripts for comprehensive Use-Case and Data Flow Analysis and review of core power models (PtPx based) along with IP core owners.
Coordinated with the HW/ SW and System teams for implementation of power optimizations and help in smooth transition of project in Post-Silicon Phase.
Gave support to customer engagement team on communication to and fro with OEM's from power perspective.
Able to manage End to End chipset cycle from Pre-Sil to Post-Sil in this timeline.
Engaged in system level power-performance trade-off analysis, tuning and optimization with multiple teams right from inception to end of project cycle.

SoC Power ManagementComputer Architecture

Associate System Engineer

Jul 2019 – Dec 2020 · 1 yr 5 mos

Chipset Power Lead for Qualcomm Snapdragon Mobile Processor : SM4250, SM4125
Received Qualstar and Orion Award.
Was able to Identify the Key Chipset Use Cases for power specific to SoC Tiering and Feature Set.
Modelled Chipset and Platform level power and setting the right power budgets for the Key KPI's in Pre-Silicon Phase.
Worked with SW and Test teams for correlation of power projected for key KPI's in Post-Silicon Phase.

SoC Power ManagementComputer Architecture