Manikandan Subramanian

CEO

Bengaluru, Karnataka, India19 yrs 3 mos experience

Highly Stable

Key Highlights

20 years of IC Design Verification experience.
Proven leadership in mentoring and team growth.
Expertise in SOC and system-level verification.

Stackforce AI infers this person is a Semiconductor Design Verification Expert with extensive leadership experience.

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Skills

Other Skills

SystemVerilogVerilogFunctional VerificationDebuggingSystem on a Chip (SoC)

About

- 20 years of hands-on experience in IC Design Verification, RTL design and silicon/FPGA bring up. - Strong DV experience at block/sub-system/SOC levels encompassing wide range of cores/protocols - Coherent interconnects/caches (CHI/ACE), DDR memory controllers (DDR3/4 RDIMM/LRDIMM), Flash, PCIe controllers (Gen4/5), storage(SAS/SATA). Extensive SOC/system level experience. - Strong blend of communication, analytical, technical and people skills. - Proven leadership qualities with track record in mentoring, growing and establishing DV teams.

Experience

19 yrs 3 mos

Total Experience

5 yrs 1 mo

Average Tenure

3 yrs 10 mos

Current Experience

Nvidia

3 roles

Principal Engineer

Promoted

Mar 2025 – Present · 1 yr 1 mo

Verification Lead

Jun 2022 – Mar 2025 · 2 yrs 9 mos

Verification Lead

Apr 2022 – Jun 2022 · 2 mos

Qualcomm

Sr Staff Engineering Manager

Oct 2020 – Mar 2022 · 1 yr 5 mos · Greater Bengaluru Area

Managed and led the NOC DV team for Bangalore Design Center.
Provided strong technical and people leadership alongside executing NOC DV across multiple product segments (automotive/mobile/VR).
Technically strengthened the DV infra and team's acumen along coherency and power verification.
Streamlined team structure for power, coherency, Top level and IP NOC features charters.
Grew the team's headcount by more than 2X along with improved inter/intra team collaboration.

Broadcom inc.

2 roles

Principal Design & Verification Engineer

Promoted

Nov 2017 – Oct 2020 · 2 yrs 11 mos

Guided development of UVC to enable faster stimulus generation for PCIE GEN5 portions of storage controller. Enable reuse of sub-system verification infrastructure along side.
Worked with architect in developing PCIE GEN5 design of the storage controller. Value add to help reduce latency, gate count and improve throughput. Worked with verification teams in thoroughly reviewing TB/verification plans.

Staff Design Verification Engineer

Aug 2015 – Oct 2017 · 2 yrs 2 mos

Enabled re-use of verification infrastructure used for ASIC sign-off flow and hardware acceleration flow (Mentor-Veloce) for FPGA. Effort helped reduce FPGA bring up time by many months
Helped DDR4 RDIMM bringup of silicon working closely with firmware and validation engineers.
Micro-architected and designed PCIE GEN4 portions of the storage controller. Worked closely with verification teams on DV closure.

Lsi

2 roles

Staff Design Verification Engineer

Promoted

Jul 2012 – Jul 2015 · 3 yrs

Lead a team of 6 verification engineers towards verification Memory Sub System (MSS) that contained industry standard and proprietary high speed interfaces connecting to DDR and Flash.
Architected a system level (constrained random/layered/parameterized) UVM TB for running accelerated commands for a storage controller SOC
Lead Verification of ARM based SATA to PCIe Bridge SOC.
Co-architected verification infrastructure for generation 2 of SOC - dual IBM PPC440 with L1/L2/L3 cache containing DDR3 (1866 MT/s), SAS(x8 12Gbps), PCIE(x8 8GT/s) and multiple proprietary HW engines.

IC Design Engineer

Jul 2006 – Jun 2012 · 5 yrs 11 mos

Designed peripheral sub-blocks - lite NAND Flash Controller and multiple protocol converter bridges. - Developed clean Spyglass flow for the design, fixing functional, Timing and Structural issues in the design
Participated in development of in-house verification methodologies
Participated in verification peripheral cores (GPIO, UART, I2C etc) using OVM