S

Sridhar K.

CEO

Bengaluru, Karnataka, India20 yrs 6 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Expert in VLSI and RTL design.
  • Led design of USB 3.0 protocols.
  • Aiming to invent Universal Peripheral Bus Protocol.
Stackforce AI infers this person is a VLSI and USB protocol expert in the semiconductor industry.

Contact

LinkedIn

Skills

Core Skills

VlsiRtl DesignUsb

Other Skills

SoCVerilogFunctional VerificationASICDebuggingSystemVerilogFPGASemiconductors

About

USB Specification Analyst, RTL Designer, Functional Verification, Prototype Debug of USB Superspeed Protocols like USB3.0. Goal is to invent Universal Peripheral Bus Protocol. Specialties: Analyze - Design - Debug - Deliver

Experience

20 yrs 6 mos
Total Experience
2 yrs 11 mos
Average Tenure
9 yrs 10 mos
Current Experience

Intel corporation

SMTS

Jun 2016 – Present · 9 yrs 10 mos · Penang Malaysia

  • Started new techno journey.
VLSIRTL designSoCUSBVerilogFunctional Verification+5

Mediatek

Lead Engineer

Aug 2014 – May 2016 · 1 yr 9 mos

  • Lead Engineer at MediaTek

Freescale semiconductor

Lead Design Engineer

Apr 2013 – Aug 2014 · 1 yr 4 mos · Bangalore

  • Networking SOC's.

Altior inc.

2 roles

Lead RTL Design

Feb 2012 – Feb 2013 · 1 yr · BANGALORE

  • Leading team of engineers, Designing world class networking and storage domain products.

Lead RTL Design

Feb 2012 – Feb 2013 · 1 yr · BANGALORE

  • Leading team of engineers, Designing networking and storage domain products.

Nvidia

Senior Design Engineer

Aug 2011 – Feb 2012 · 6 mos · Bengaluru, Karnataka, India

  • Involved in the Tegra SOC. Contributions on USB3.0 DRD Controllers.

Whizchip design technologies pvt ltd

Senior Engineer VLSI Design

Jul 2011 – Aug 2011 · 1 mo · BANGALORE

  • Design and Development of Digital IP's.

Innovative logic india pvt ltd

Senior Design Engineer

Sep 2006 – Jun 2011 · 4 yrs 9 mos · BANGALORE

  • Participated and Designed couple of IP's like WUSb, USB 3.0 Device, USB 3.0 Host Controllers.
  • Specification --> RTL --> Verification --> Prototyping.

Body drench india pvt ltd

Technical Engineer

Sep 2004 – Jan 2006 · 1 yr 4 mos · Mumbai

  • Technical Engineer.

Education

VEDANT ISRO Chandigarh Mohali.

VLSI DESIGN — VLSI

Jan 2006 – Jan 2006

Anna University Chennai

BTECH — Electronics and Communication Engineering

Jan 2000 – Jan 2004

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