Arpan Sarkar — Software Engineer

May’11-Nov’12 with Interra Systems, Bangalore Growth Path: May11-Aug’11 Trainee Aug’11-Nov’12 Design Engineer (E3) –Client: Texas Instruments, Bangalore Key Result Areas: As Trainee: Underwent the training on: Verilog using ModelSim Memory Designing and Characterization Carried out the project of Vending Machine (from FSM) using Verilog Deftly worked on tools used during training like HSpice and ICFB for schematics As Design Engineer (E3): Looked after the characterization of the Standard Cell Library (GS70) using TerboChar for both HVT and SVT cells.And released the data in TK-CML format after IQC (Integrated Quality Check) Handled the LP50 cells Characterization using Altos Liberate (now acquired by cadence) for 27 PTV's Skilfully used Starxt tool, for extraction of netlist from the given laffs Developed required setup for IQC, and start with IQC from the same list of cells July’13- Present with DXCorr Design Inc, Bangalore Growth Path: July’13-July'14 Associate Member of Technical Staff (AMTS) 1) Renesas HP Memory Compiler in Renesas 40s technology. Generation of compiler instances, simulation and validation of instances and characterization of the same. 2) TSMC 28HPM Data Sheet Preparation 3) TSMC 28HPM memory instance design and analysis.Generating critical path netslist , simulation , doing Monte carlo simulations for Writability and Sense Amplifier analysis Aug’14- Immensa Semiconductors, Bangalore Growth Path: Aug’14-April'15 Design Engineer (Memory Developments) 1) Complete ownership of margin analysis and characterization of TSMC 28HPM low dynamic power SRAM. 2) Bit cell and sense amplifier analysis using Monte Carlo simulations 3) Debugging of SRAM silicon issue for Texas Insruments.

Stackforce AI infers this person is a Semiconductor Design Engineer with expertise in Memory Design and Characterization.

Experience: 14 yrs