Gaurav Kaushik — CTO

I am a seasoned SoC design engineer and manager with approximately 19 years of experience. My primary skillset revolves around timing closure (STA) and managing the entire sub-system/SoC process, from synthesis to GDS. My experience spans across various sub-NM technologies, including 3nm, 7nm, 10nm, 14nm, 16nm, 28nm, 45 nm, 65 nm, and 90nm. I hold an M.TECH degree focusing on VLSI Design from Dhirubhai Ambani Institute of Information and Communication Technology in Gandhinagar, India. My experience broadly covers the following aspects of VLSI design. In my role as SOC/SS lead, I am responsible for leading the design of system-on-chip (SoC) and system solutions (SS) from the Register Transfer Level (RTL) to GDS. I resolve cross-domain issues and collaborate with architects, IP, and integration teams to address backend (BE)/IP issues. Additionally, I am involved in top-level abutted design floor-planning, timing budgeting, full chip/SS clock and data flow planning, and late functional ECOs. As an STA expert, I have experience in constraints development, clock balancing, I/O budgeting, full-chip and partition level timing signoff, pre-CTS/post-CTS timing analysis, timing margins analysis for signoff, CDC, SCAN, resets, timing ECOs, and ETMs-based design delivery. As an SD lead, I managed the synthesis flow and optimizations, addressed low-power design issues, developed the ISO/LS cell strategy, implemented UPF flow, and planned odd-shaped partitions. I have experience in designing floor plans, placement, and conducting CTS reviews.

Stackforce AI infers this person is a Semiconductor Design Expert with extensive experience in SoC development and timing analysis.

Location: Bengaluru, Karnataka, India

Experience: 19 yrs 5 mos