raghuram iyer

CTO

Bengaluru, Karnataka, India20 yrs experience

Highly Stable

Key Highlights

Expert in GPU architecture and performance verification.
Led multiple successful SOC projects from inception to verification.
Strong background in high-speed memory subsystem design.

Stackforce AI infers this person is a Semiconductor Architect specializing in GPU and SOC performance verification.

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Skills

Core Skills

Gpu ArchitecturePerformance VerificationSoc Architecture

Other Skills

ASICCDL performance analysisDigital ElectronicsFPGAGPU memory subsystem architectureICMulti GPU scalingNVLINKRTL designSoCSystemVerilogTegra SOCdebuggingfunctional modeling

Experience

Nvidia graphics pvt. ltd.

2 roles

GPU memory subsystem architecture manager

Apr 2016 – Present · 9 yrs 11 mos · Bengaluru Area, India

We are hiring !!
Manage the GPU memory subsystem architecture team in Bangalore. This includes the architecture of units in the memory sub system (HSHUB / GPCARB ) , performance verification of the memory units ( High speed hub, L2 , memory controller etc), a bunch of studies and modeling for future GPUs.
Started off a team to look into issues with Multi GPU scaling, especially in memory and enhancing the architectures. The scope of the work includes analyzing perf for DL / MLPERF / single node / at scale .

GPU memory subsystem architectureperformance verificationMulti GPU scalingDL performance analysisGPU architecturePerformance verification

Senior Architect

Jan 2006 – Jan 2016 · 10 yrs · Bengaluru Area, India

Worked on the high speed HUB architecture, NVLINK. This includes architecting the unit from scratch, writing functional models, debugging functional and performance issues. All of that resulted in unit without any bugs / issues once the silicon arrived.
Lead the Tegra SOC performance verification effort. There was no infrastructure / plan / methodology in place. I lead the team that set up the infrastructure / methodology / testplan / testing for this effort.
Lead the GPU performance verification when placed in Tegra. There was lot of effort involved as this was the first chip with the new GPU placed in the Tegra.
Worked on the GPU performance verification effort in Kepler class of GPUs. Learnt a lot about the GPU and its functionality during this effort.
Architected SATA for the new set of features in a range of MCP chips.
Worked on class random verification effort.
Started off career with performance verification of SATA and PCIE.

high speed HUB architectureNVLINKfunctional modelsperformance verificationTegra SOCPerformance verification+1