Chetan G.

Software Engineer

Bengaluru, Karnataka, India11 yrs 9 mos experience

Highly Stable

Key Highlights

Over 11 years in memory design validation.
Expert in memory characterisation and design verification.
Strong mentoring skills in semiconductor engineering.

Stackforce AI infers this person is a Memory Design Engineer with expertise in semiconductor technology.

Contact

chetan.ganiger27@gmail.com LinkedIn

Skills

Core Skills

Memory Design ValidationDesign VerificationSimulation SoftwareMemory CharacterisationTiming ValidationMemory Layout DesignPhysical VerificationTiler CodingDigital DesignAsic Flow

Other Skills

BashPoweronSRAMScriptingESPCVProblem SolvingROMTeam MentoringCommunicationShell ScriptingMicrosoft ExcelCadence VirtuosoLayout Versus Schematic (LVS)Verification using VerilogFullcustom Flow

About

11 plus years of experience in memory design validation, characterisation, and scripting to ensure the quality and performance of various memory compilers in different technology nodes. I am passionate about learning new technologies and skills, and contributing to the innovation and growth of the semiconductor industry.

Experience

11 yrs 9 mos

Total Experience

1 yr 8 mos

Average Tenure

Current Experience

Broadcom inc.

IC Design Engineer

Aug 2019 – Jan 2024 · 4 yrs 5 mos · Bengaluru, Karnataka, India · On-site

BashPoweronSRAMScriptingESPCVDesign verification+7

Frenus tech pvt ltd

Senior Design Engineer

Jul 2017 – Jul 2019 · 2 yrs · Bengaluru Area, India · On-site

Problem SolvingCommunicationSimulation SoftwareMemory Design ValidationESPCVPoweron+3

Mediatek

Engineer

May 2015 – Jul 2017 · 2 yrs 2 mos · Bengaluru Area, India · On-site

Memory Characterisation, APL models, Timing Validation, Tiler and Netlister, Shell Scripting

Problem SolvingLayout Versus Schematic (LVS)CommunicationSimulation SoftwareMemory CharacterisationTiming Validation

Immensa semiconductors

Design Engineer

Aug 2014 – Apr 2015 · 8 mos · Bengaluru Area, India

Worked on Memory Layouts in technology nodes 55nm 28nm. Basic Scripting for layout automation and shell scripting for Physical verification and QA.

Problem SolvingLayout Versus Schematic (LVS)CommunicationSimulation SoftwareMemory Layout DesignPhysical verification

Dxcorr hardware technologies

Memory Layout Design Engineer (AMTS)

Jul 2013 – Jul 2014 · 1 yr · Bengaluru Area, India

Experienced in Tiler coding to stitch the memory layouts (Place and Route).
Designed Memory Leaf Cells, Did Tiler coding for memory Block layouts like Control, Global Control, IO, Global IO for the HD Memory Compiler in 40nm,
Did the Top level Memory Instance for a register file in 28nm,
Did leaf Cell layouts in 16 nm FinFet.

Problem SolvingLayout Versus Schematic (LVS)CommunicationMemory Layout DesignTiler coding

Rv-vlsi design center

ASIC Design Trainee

Jan 2013 – Jul 2013 · 6 mos · Bengaluru Area, India

Completed a PG Diploma course "An Advanced Diploma in ASIC design" at RV-VlSI Design Center Bengalooru India.
Acquired Skills like Digital Design and Verification using verilog, ASIC Flow, Fullcustom Flow, RTL to GDS, Place and route flow. Standard Cell Layout design, Specialized in Standard Cell Layout Design.
Drawn Standard Cells in 90nm technology and Precharge block of SRAM memory in 28nm as part of the Project. Learnt About Memory Architecture.
Did Mini projects on Design and Verification using verilog, STA and P&r.

Layout Versus Schematic (LVS)Communication