R

R C.

Software Engineer

Portland, Oregon, United States17 yrs 6 mos experience
Highly StableAI Enabled

Key Highlights

  • Expert in USB and PCIe protocol development.
  • Proficient in System Verilog and UVM for verification.
  • Hands-on experience with compliance testing for product certification.
Stackforce AI infers this person is a specialist in VLSI and FPGA design with a focus on verification and compliance.

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Skills

Core Skills

Verification Ip DevelopmentProtocol Knowledge

Other Skills

ASICAlteraArtificial Intelligence (AI)CChip/Core Level UVM Environment creation for DUT as Host/Device/PHY combinationsCommunicationEDAEmbedded SystemsFPGAField-Programmable Gate Arrays (FPGA)Functional VerificationGPIOGitHub CopilotGroup DynamicsI2C

About

Specialties: Strong protocol knowledge on PCIe, USB[USB1.0/USB2.0/USB3.0/USB3.1/USB3.2/USB4/xHCI Driver/Device Driver], AMBA[APB/AHB/AXI], UART, GPIO and I2C etc. Hands on experience in System Verilog/Verilog/VHDL/UVM/OVM/VMM based Verification IP[Protocol Different Layers/Monitor/Checker/Scoreboard/Coverage components] development from scratch. Strong knowledge of Synopsys DesignWare USB [DUT as Host/Device/PHY(UTMI, ULPI, eUSB2.0, PIPE3, PIPE4, PIPE5, PIPE6)], I2C, UART and GPIO IP programming, System Verilog/UVM based driver development and integrations. Experienced in IP Core micro architecture design, RTL Design, Synthesis, STA, Functional Simulation, Board Testing and design verification/Validation using Altera FPGA[SOPC Builder and NIOS-II]. Hands on experience in usb.org compliance testing[software testing using CV TOOL and electrical specification testing on board] for product certification.

Experience

Microsoft

IP/SubSystem/SoC Verification Engineer

Oct 2021Present · 4 yrs 5 mos · United States

System VerilogVerilogVHDLUVMOVMVMM+7

Intel corporation

Pre-Silicon IP Validation Manager

Jun 2021Oct 2021 · 4 mos · United States

Synopsys inc

R & D Engineer, Staff (Verification Group)

May 2011Jun 2021 · 10 yrs 1 mo · United States

System level solutions ( india ) pvt. ltd

JR. IP Design Engineer

Sep 2008Apr 2011 · 2 yrs 7 mos · Gujarat, India

Education

Centre for Development of Advanced Computing (C-DAC)

DVLSI — VLSI Frant End & Back End Design

Jan 2008Jan 2008

Veer Narmad South Gujarat University, Surat

B.E — EC & CO

Jan 2004Jan 2007

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