Nidhi Padiya

Software Engineer

Bengaluru, Karnataka, India11 yrs 3 mos experience

Highly Stable

Key Highlights

Expert in FPGA verification and design methodologies.
Proficient in System Verilog and UVM for ASIC verification.
Strong background in HBM and DDR protocols.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in FPGA and ASIC design methodologies.

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Skills

Core Skills

Fpga VerificationSystem VerilogUvm

Other Skills

VivadoPythonVIPAPBAXIXilinx VivadoVHDLPerlCC++VerilogLinuxDDR2Agile MethodologiesHBM

About

ASIC Verification Engineer Skills: • Hardware Description Language : Verilog • Hardware Verification Language : Systemverilog • Verification Methodology : UVM • Protocols : DDR2, HBM2, AXI, APB • Scripting Language : Perl, Python, Makefile • Programming Language : C, C++ • OS : Linux, Windows • Version Control : SVN, CVS, Perforce • Tools : Questasim, VCS, Cadence xrun, Simvision, IMC, Vivado

Experience

11 yrs 3 mos

Total Experience

4 yrs 5 mos

Average Tenure

2 yrs 4 mos

Current Experience

Samsung semiconductor

Senior Staff Engineer at Samsung Semiconductor India Research

Jan 2024 – Present · 2 yrs 4 mos · Bengaluru, Karnataka, India

Amd

Senior Silicon Design Verification Engineer

Jun 2021 – Jan 2024 · 2 yrs 7 mos · Hyderabad, Telangana, India · On-site

Full chip level FPGA verification for CPM (Coherency & PCIe Module) block.
Design creation using Vivado.
Testplan creation, development & TB update based on device specification.
Debugging & resolving Failures.
Performance improvement to reduce simulation time.
PCSR (Programmable control & status register) VIP implementation & enhancement based on device specification.

FPGA verificationSystem Verilog

Einfochips

Senior ASIC Verification Engineer Level 2

Jan 2015 – May 2021 · 6 yrs 4 mos · Ahmedabad Area, India · On-site

HBM controller verification using System verilog and UVM.
Scoreboard implementation & enhancement.
Full ownership of functional coverage planning, implementation, analysis & closure.
Code coverage analysis.
Integration of different vendors VIP into Testbench.
Test plan development and Identification of protocol checks.
Test cases and protocol checks development.
UVM based VIP development.
GUI development using Python.
Testcase Debugging.

System VerilogUVM