Dimittri D.

Software Engineer

Bengaluru, Karnataka, India6 yrs 9 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Experienced in ASIC design and verification.
Proficient in Functional Verification methodologies.
Hands-on experience with RTL coding and UVM.

Stackforce AI infers this person is a Semiconductor Verification Engineer with expertise in ASIC and Functional Verification.

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Skills

Core Skills

Functional VerificationAsic

Other Skills

Universal Verification Methodology (UVM)SVFPGA verificationpower assertionssensor related bugsRTL CodingVerilogPerlUVMData StructuresApplication-Specific Integrated Circuits (ASIC)ScriptingDigital ElectronicsC (Programming Language)Python (Programming Language)

About

Engineering professional working as a Verification Engineer with Ciena India RSP team || AMD || Completed Internship in CIP group at Intel Technology Pvt. Ltd. Bangalore || Passionate to explore digital & analog domain. Skilled with hands-on experience in Functional Verification with Router Asic/Ip platform , NoCs and IP level-subsystems. Wrote Testbench in UVM. Developed RTL Code for basic-models. Automated Scripts with Perl. At Ciena, Worked on multiple Network switch modules , thermal blocks , power scenarios. At AMD, I had worked in Core CPU-Rtl Verification by analysing, debugging the Architectural level failures, errors. || At Intel, I was involved in ASIC Design and Verification.

Experience

6 yrs 9 mos

Total Experience

2 yrs 3 mos

Average Tenure

3 yrs 8 mos

Current Experience

Intel corporation

Design Verification Engineer

Sep 2022 – Present · 3 yrs 8 mos · Bengaluru, Karnataka, India

Universal Verification Methodology (UVM)SVFunctional VerificationASIC

Ciena

Hardware Engineer

Jul 2020 – Aug 2022 · 2 yrs 1 mo · Gurugram, Haryana, India

Verified FPGA blocks , power assertions , sensor related bugs

FPGA verificationpower assertionssensor related bugsFunctional Verification

Amd

Verification Engineer

Jul 2019 – Jun 2020 · 11 mos · Bengaluru Area, India

Cpu verification Engineer

Functional Verification

Verifiq technologies private limited

Verification Engineer

Jul 2019 – Jun 2020 · 11 mos · Bengaluru Area, India

Intel corporation

Component Design Intern

Jul 2018 – Jul 2019 · 1 yr · Bengaluru Area, India

The internship involves IP Level verification and design of Blocks for 5G Trace and Debug Sub System of a SoC. It is the front end pre-silicon validation team working with functional and formal verification.
My work involved basic RTL Coding using HDLs. During my internship I have worked on designing of adders ,FIFO,FSMs,sequence detector, etc using RTL Coding, writing directed Testbenches in Verilog & SV.
I have contributed towards NoC sub-system by writing a Perl script for comparing NIU parameters in design with Specifications in Excel Sheet. The NIUs are configurable via different parameters.Created the Perl script for comparing these NIU parameters used in design vs required specification.
As a standalone project, I have done RTL coding for design of a small Router using SV & verified the same using Universal Verification Methodology.
Have worked with modifying input values for test cases and checking their Pass/Fail case.
Presently, I am working on the basics of target filter of NoC .

RTL CodingVerilogSVPerlASICFunctional Verification