Jyoti Kumari

Software Engineer

Bengaluru, Karnataka, India13 yrs 7 mos experience
Most Likely To SwitchAI ML Practitioner

Key Highlights

  • Over 12 years of experience in ASIC/SOC/IP verification.
  • Expertise in UVM-based CRV environments.
  • Led verification for complex IPs including PLLs and DDR protocols.
Stackforce AI infers this person is a Semiconductor Verification Engineer with extensive experience in ASIC and IP verification.

Contact

LinkedIn

Skills

Core Skills

Rtl VerificationFunctional Verification

Other Skills

Synopsys toolsDebuggingUniversal Verification Methodology (UVM)System VerilogAXIVHDLCVerilogVLSIUVMC++PerlUnixOOPLinux

About

12+ years of industry experience in ASIC/SOC/IP verification with specialization in UVM based CRV environment.Srong expertize in verifing complex IPs including PLLs, DDRPHY, DMA,Multimedia subsytems.

Experience

13 yrs 7 mos
Total Experience
3 yrs 4 mos
Average Tenure
4 yrs 6 mos
Current Experience

Amd

MTS Silicon Design Engineer

Nov 2021 – Present · 4 yrs 6 mos · India · On-site

  • - Verification Lead for PLL.
RTL VerificationFunctional Verification

Intel corporation

Senior Verification Engineer

Mar 2018 – Oct 2021 · 3 yrs 7 mos · Bangalore Urban, Karnataka, India · On-site

  • Worked in verification of DDR4 and DDR5 protocols.
  • Created TB components like sequences and assertions for new fratures as per protocol.
  • Regression debug, worked with RTL team to root cause issues.
  • Guided junior engineers on DDR protocol and verification techniques.
  • Worked on migration of legacy VMM verification environment to UVM.
RTL VerificationFunctional Verification

Mediatek

Senior Verification Engineer

Aug 2014 – Feb 2018 · 3 yrs 6 mos · Bangalore · On-site

  • Worked on verification of multiple IP's like GDMA, Logger, Multimedia Subsystems
  • Worked on creating CRV environments.
  • RAL verification, functional and code coverage analysis.
RTL VerificationFunctional Verification

Tata consultancy services

System Engineer

Jul 2012 – Jul 2014 · 2 yrs · Bangalore

  • AXI bridge ( AXI upsizer and downsizer) - Used when narrower/wider master talks to narrower/wider slave.
  • Created reusable test cases,sequnces and scoreboards for AXI txns.
  • Worked on functional coverage implementation analysis.
RTL VerificationFunctional Verification

Education

SRM,Chennai

Master's Degree — VLSI Design

Jan 2010 – Jan 2012

University of Rajasthan

Bachelor's Degree

Jan 2006 – Jan 2010

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