Mar 2017 – Feb 2020 · 2 yrs 11 mos · bangalore

• Explored path of Soc And IP level ASIC verification ,exercised most of the work in verification by using advanced methodologies like UVM & System verilog. Experienced two tape outs ,which has given enough knowledge of Vision related algorithms,processors of various variety as Enscillca and synopsys.
• work was challenging because some were dual core and multi-processor .

Dec 2016 – Feb 2017 · 2 mos · Bengaluru Area, India

• Opportunity to work around of AMBA -AXI bus , were i am able to exercise some of featurelike outstanding ,out of order and able to write the driver and monitor components in UVM.

Sep 2016 – Nov 2016 · 2 mos · bangalore

• Writing RTL(IP) and verifying through (System Verilog and UVM) methodologies,
• SPI(serial to prallel communication),
• ROUTER 1x3 (one master and 3slaves),
• currently working on AHB-APB Design through XILINX.
• with assertion ,code coverage,functional coverage.