Santhosh Sheelam — Software Engineer
=> Got trained in Veda IIT for 6 months in Logic Design => Known HDL languages are Verilog, System Verilog, UVM => Known programming languages are C,C++,Core JAVA,HTML => Known scripting languages are PERL,TCL => Can use Windows,Linux operating systems
Stackforce AI infers this person is a Digital Design Engineer specializing in Functional Verification and RTL methodologies.
Location: Hyderabad, Telangana, India
Experience: 8 yrs 10 mos
Skills
- Functional Verification
- Rtl Verification
Career Highlights
- Lead Design Engineer with extensive HDL expertise.
- Proficient in multiple programming and scripting languages.
- Strong background in functional and RTL verification.
Work Experience
Cadence Design Systems (India) Pvt. Ltd.
Lead Design Engineer (2 yrs 8 mos)
AMD
Senior silicon design Engineer (1 yr 3 mos)
Intel
Soc verification engineer (2 yrs 5 mos)
SOCTRONICS TECHNOLOGIES PRIVATE LIMITED
ASIC verification Engineer (2 yrs 6 mos)
Education
Engineer’s Degree at JNTUH College of Engineering Sultanpur
Intermediate at NRI Junior College
High School at Jawaharlal Nehru Technological University