Tej Kothari — Software Engineer

With nearly six years of experience as an ASIC Design Engineer at Microsoft, I have been deeply involved in front-end digital design, specializing in security IP development. My expertise spans RTL design, CDC/RDC analysis, UPF, and synthesis, working across advanced technology nodes such as 3nm, 5nm, and 12nm. I have played a key role in designing and implementing secure and power-efficient architectures, including a CPU core RNG, post-quantum crypto engine, an ultra-low power real-time clock, and secure cache systems with encryption. My work on integrating third-party CPU cores and implementing JTAG security features has strengthened silicon security against potential vulnerabilities. Additionally, I have contributed to the bring-up and validation of security IP, collaborating cross-functionally to ensure robust and high-performance designs. Passionate about innovation in ASIC and security hardware design, I am always eager to tackle complex design challenges and advance secure silicon architectures. Let’s connect!

Stackforce AI infers this person is a skilled ASIC Design Engineer with a focus on security hardware.

Location: San Jose, California, United States

Experience: 7 yrs 8 mos