Oct 2017 – Apr 2022 · 4 yrs 6 mos · Bengaluru, Karnataka, India

• Head of HW division and Bangalore site-head. Switched from semiconductor to finance (HFT/prop-trading/algo-trading) industry.
• ● Built HW team and EDA compute infra from ground-up.
• ● Led end-to-end HW development, verification and back-end teams and projects.
• ● Developed FPGA-based (Xilinx Ultrascale+) high frequency trading solutions for in-house traders.
• ● Successfully executed multiple projects across various exchanges (NSE/BSE/BVMF) resulting in a significant increase in company profitability.

Jul 2015 – Oct 2017 · 2 yrs 3 mos

• Delivered modem subsystem to SDM630, SDM660 and SDM670 SoCs.

Mar 2011 – Jul 2015 · 4 yrs 4 mos

• Member of modem digital HW design team.
• Designed various subsystems on multiple Qualcomm modems - MSM8974, MDM9x25, MDM9x35, MDM9x45, MDM9x55 and WTR5K

Jan 2008 – Nov 2010 · 2 yrs 10 mos · Greater Boston

• ● Developed micro-architectural design specification, created RTL design (verilog) with focus on low power, ensured that designed functions met specifications. Optimized power consumption (used Synopsys’ Primepower, Apache’s Powertheater), did formal comparisons (used Synopsys’ Formality/Cadence LEC) between RTL/post-synthesis/post-layout designs, ran lint (spyglass). Debug and fix any timing failures (used Primetime).
• ● Designed System bus interface unit to interface Blackfin DSP data and instruction cache ports (core-connect protocol) to an external memory with an AHB interface.
• ● Designed multiple synchronous/asynchronous bridges interfacing buses with different protocols.
• ● Wrote, debugged ARM9 C & assembly level testcases
• ● Implemented and verified multiple ECOs to fix HW bugs found in post tapeout silicon. Helped backend resolve any timing issues introduced by ECOs.
• ● Generated test vectors for manufacturing group for ATE testing.
• ● Board level debug of DBB (digital baseband) silicon with the aid of logic analyzer to find root cause behind SW crash.
• ● Knowledge of Cadence low power (CLP) flow – performed structural checks on RTL level designs – checked for correct placement of isolation cells, level shifters, proper signal crossings between ON/OFF power domains etc.

Jul 2004 – Dec 2007 · 3 yrs 5 mos · Greater Boston

• ● Designed External Coprocessor Interface (ECPI) module - master/slave - 15K/12K gates, provides a bidirectional communication infrastructure between Digital Baseband (DBB) and any coprocessor chip mastered from DBB, 130 MB/s of raw data transfer capacity. Efficiently transfers data across three asynchronous clock domains. Multiple Read/Write channels to handle parallel data streams, can prioritize between various channels on-the-fly, flow control between master and slave, dynamic clock gating to save power.
• ● Supported DV, created testbenches – full chip verification, module level (PLL, ECPI) verification, performed logic simulation, debug RTL/gate level simulations.
• ● Hardware testing: conducted voltage scaling experiments on silicon to ensure ECPI performance, ran various c testcases on silicon to resolve vector issues.

Sep 2002 – Jun 2004 · 1 yr 9 mos · Greater Madison Area

• ● Designed & implemented Bluetooth Baseband, LM and HCI conforming to Bluetooth Spec. V1.1 with UART as Host interface. Complete system coded in Verilog, LMP and HCI were implemented as software layers (Assembly).
• ● Baseband components - Packet Composer & Decomposer, Frequency Hop generator, Time-base generator, Access code generator/correlator, Interface to Processor and Link controller. Authentication Algorithm Safer-128 implemented in hardware.
• ● Designed a custom RISC processor with a small instruction set and interrupt support, wrote an Assembler for the same. Successfully tested the system in hardware on FPGA.