Prateek Gupta

Software Engineer

Bengaluru, Karnataka, India15 yrs 9 mos experience

Highly Stable

Key Highlights

Expert in Static Timing Analysis and RTL Design.
Proven track record in DFT methodologies.
Extensive experience in semiconductor industry.

Stackforce AI infers this person is a Semiconductor Engineering Expert with a focus on Timing Analysis and Design for Test.

Contact

Skills

Core Skills

Static Timing AnalysisRtl DesignDft

Other Skills

JTAGI2CSoCVerilogEthernetAMBA AHBTimingATPGMatlabEnglishResearch

Experience

15 yrs 9 mos

Total Experience

5 yrs 6 mos

Average Tenure

4 yrs 9 mos

Current Experience

Cypress semiconductor corporation

Principal Engineer

Aug 2021 – Present · 4 yrs 9 mos · Bengaluru, Karnataka, India

Static Timing AnalysisJTAGI2CSoCDFTVerilog+5

Mediatek

2 roles

Sr Staff Engineer

Jun 2018 – Aug 2021 · 3 yrs 2 mos

Staff Engineer

Mar 2015 – May 2018 · 3 yrs 2 mos

Freescale semiconductor

Senior Design Engineer

Jul 2010 – Mar 2015 · 4 yrs 8 mos

Static timing analysis for SOC's at 90 , 55 and 28 nanometer.
Generated timing constraints for Functional and DFT modes like ATPG, LBIST , MBIST etc.
Timing constraints for IO protocols like display ( RSDS , raw RGB, Open LDI) , Quadspi , DSPI, JTAG, Ethernet, Nexus, TRACE, I2S, I2C, MLB
Designed clock tree for complex functional and DFT architectures.
Basic Understanding of AMBA AHB, APB and AXI protocols.

Static Timing AnalysisATPGJTAGEthernetI2CAMBA AHB+1

Education

National Institute of Technology Kurukshetra

Bachelor of Technology (B.Tech.)

Jan 2006 – Jan 2010

Anandalaya Education Society

Senior Secondary examination

Jan 1994 – Jan 2006

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