Satish Gupta

Product Engineer

Bengaluru, Karnataka, India11 yrs 8 mos experience

Highly Stable

Key Highlights

Expert in SV and UVM for ASIC verification.
Strong background in ORAN and JESD protocols.
Proven track record in firmware automation and debugging.

Stackforce AI infers this person is a semiconductor verification expert with strong skills in design and automation.

Contact

Skills

Core Skills

SystemverilogUvm

Other Skills

CORANJESDAXIVCSverdiGITDSSCLSFnetbatchFirmware AutomationDebuggingMatlabEmbedded SystemsExpress PCB

About

Design Verification Engineer with a demonstrated history of working in the semiconductors industry. Skilled in SV, UVM, JESD, ORAN, PCIe RTL Debugging, and C (Programming Language). TB development and maintenance. Coverage activities. Exposure to GLS, formal verification. Strong engineering professional with a Master of Technology (M.Tech.) focused in Advanced communication systems from National Institute of Technology Warangal.

Experience

11 yrs 8 mos

Total Experience

5 yrs 4 mos

Average Tenure

1 yr

Current Experience

Cadence

Principal Design Engineer

May 2025 – Present · 1 yr · Bengaluru, Karnataka, India

Intel corporation

3 roles

Design Verification Engineer

Apr 2024 – Mar 2025 · 11 mos

Pre-Si Valid/Verif Engineer

Promoted

Jun 2022 – Apr 2024 · 1 yr 10 mos

Design Verification Engineer

Jul 2015 – Jun 2022 · 6 yrs 11 mos

part of multiple asic/design verification of blocks using SV-UVM based testbenches. Major languages: UVM, SV, C.
Specialized in ORAN/XRAN, JESD, and AXI protocols.
Tools: VCS verdi, GIT, DSSC, LSF, netbatch,

SystemVerilogUVMCORANJESDAXI+6