Apr 2023 – Apr 2025 · 2 yrs · Bengaluru, Karnataka, India · On-site

Apr 2020 – Apr 2023 · 3 yrs · Bengaluru, Karnataka

Dec 2018 – Apr 2020 · 1 yr 4 mos · Bangalore

• Went through intense training program to learn modern 64-bit computer architecture at micro level.
• Familiar with various types of assembly based test cases and test suits.
• Familiar with directed test cases and random test cases.
• Familiar with scripting commands for running various test cases and generating log files.
• RTL debugging with basic log files plus regenerated log files and with the help of waveforms.
• Good hand in debugging of unique signatures and filling them with proper documentation.
• Decent hand in writing scripts for automatic marking.

Jul 2018 – Apr 2020 · 1 yr 9 mos · Bangaon Area, India

Oct 2016 – May 2018 · 1 yr 7 mos · Bangaon Area, India

• Project#1 Verification IP Development for AXI Protocol using System Verilog
• Responsibilities:
• Develop VIP architecture to be compatible with both master and slave behavior
• List down AXI features and develop testplan
• Develop AXI VIP components
• Integrated AXI master VIP with slave VIP
• Develop functional tests and debug the same
• Regression setup and closing of VIP validation using coverage criteria
• Project#2 Verification IP Development for AHB Protocol using System Verilog
• Responsibilities:
• Develop UVC architecture to be compatible with both master and slave behavior
• List down AHB features and develop testplan
• Develop AHB UVC components
• Integrated AHB master UVC with slave UVC
• Develop functional tests and debug the same
• Regression setup and closing of UVC validation using coverage criteria
• Project#3 Design and Verification of SPI Controller using UVM
• Responsibilities:
• Listing down design features
• Setting up testbench and testbench component coding
• Testplan development
• Testcase coding