Robin George

Director of Engineering

Bengaluru, Karnataka, India26 yrs 4 mos experience
Most Likely To SwitchHighly Stable

Key Highlights

  • Over 20 years of semiconductor industry experience.
  • Expert in functional verification and complex project delivery.
  • Proven leadership in cross-functional team management.
Stackforce AI infers this person is a semiconductor industry expert with a strong focus on functional verification and design engineering.

Contact

Skills

Core Skills

Functional VerificationProject ManagementAsicDesign Engineering

Other Skills

DDR5 PHY RTL design/verificationcross-functional team leadershipformal verificationstakeholder communicationASIC verificationcross-functional collaborationWiFi/Bluetooth SoCsreporting and documentationtestbench developmentfunctional coverageKPI reportingModem Sub-System VerificationUVMUVM methodologyASIC-level DV

About

Robin George is a Director of Silicon Design at AMD, with over 2 decades of experience in the semiconductor industry. He is a functional verification expert, with a track record of delivering high-quality and complex projects across multiple domains, such as SOCs, DDR5, 3D graphics, flash memory, DFX, and automotive. He has a strong technical background in design and verification, with proficiency in RTL implementation, formal verification, CRV, and directed verification across IP, subsystem, and SOC levels.

Experience

26 yrs 4 mos
Total Experience
3 yrs 3 mos
Average Tenure
3 yrs 8 mos
Current Experience

Amd

Director Silicon Design - Data Fabric

Sep 2022Present · 3 yrs 8 mos · Bengaluru, Karnataka, India

Synopsys inc

Sr Manager

May 2017Sep 2022 · 5 yrs 4 mos · Bengaluru, Karnataka, India · On-site

  • Led cross-functional teams through full verification lifecycle, working on DDR5 PHY RTL design/verification and managed complex schedules, mentoring, and stakeholder communication. Championed formal verification adoption, delivered a multi-protocol DDR PHY under tight timelines, and oversaw audits and internal coordination. Setup RTL design team in India for the DDR5 PHY.
DDR5 PHY RTL design/verificationcross-functional team leadershipformal verificationstakeholder communicationproject managementFunctional Verification+1

Microchip technology

Manager - Verification

Oct 2015Apr 2017 · 1 yr 6 mos · Bangalore, India

  • Managed ASIC verification with cross-functional collaboration to deliver high-quality silicon. Led verification for WiFi/Bluetooth SoCs and IPs, expanding the team from 2 to 12. Owned end-to-end verification for two SoC projects and handled reporting and documentation.
ASIC verificationcross-functional collaborationWiFi/Bluetooth SoCsreporting and documentationFunctional VerificationASIC

Mediatek

Verification Manager

Sep 2014Oct 2015 · 1 yr 1 mo · Bangalore

  • Managed testbench development, functional coverage, and KPI reporting. Spearheaded Modem Sub-System Verification across 2G/3G/4G LTE, ARM cores, and AMBA buses, and took full ownership of smartphone MSS verification using UVM. Led enhancing engineering methodologies and validating ASIC-level low power flows using CPF (RTL/GLS).
testbench developmentfunctional coverageKPI reportingModem Sub-System VerificationUVMFunctional Verification+1

Sandisk

Verification Manager

Jan 2013Sep 2014 · 1 yr 8 mos · Bangalore, India

  • At SanDisk, I led functional verification of Flash memory controller ASICs, applied UVM methodology and executed ASIC-level DV (RTL/GLS) using C/Verilog-based environments.
functional verificationUVM methodologyASIC-level DVC/Verilog-based environmentsFunctional VerificationASIC

Amd

Manager Design Engineering

Mar 2007Jan 2013 · 5 yrs 10 mos · Bangalore, India

  • At AMD, I led DFX verification across multiple x86-based APU SoCs (CPU+GPU) including Fusion and Server families. As Manager Design Engineering, I scaled and managed a 16-member team, driving full SoC DFX verification and global methodology improvements. I also served as technical lead for DFT verification and held end-to-end ownership of design verification activities.
DFX verificationSoC DFX verificationglobal methodology improvementsFunctional VerificationDesign Engineering

Intel

Component Design Engineer

May 2004May 2006 · 2 yrs

  • 3D gfx design verification.

Motorola semiconductor

Sr Design Engineer

Jan 1999Apr 2004 · 5 yrs 3 mos · Gurugram, Haryana, India

  • IP and SOC level functional verification across many Wireless, Automotive and Printer products.

Education

Indian Institute of Management, Kozhikode

eMDP — Senior Management Program

Jul 2021Aug 2022

Rajiv Gandhi Institute of Technology, Kottayam

B Tech — EC

Jan 1994Jan 1998

Kerala Education Society

Jan 1981Jan 1994

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