Niraj Jain

Software Engineer

Mumbai, India16 yrs 4 mos experience

Most Likely To SwitchHighly Stable

Key Highlights

Expert in VLSI and embedded systems design.
Proven track record in semiconductor IP verification.
Strong experience in high-speed memory design.

Stackforce AI infers this person is a Semiconductor and Telecommunications expert with extensive experience in VLSI and SoC design.

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Skills

Core Skills

VlsiEmbedded SystemsVerilogDesign OptimizationRtl VerificationIp VerificationIc DesignModel VerificationDesign EngineeringMemory VerificationSoc VerificationValidation

Other Skills

VHDLFPGACEmbedded SoftwareTiming characterizationPower characterizationMargin analysisCode coverage analysisGate level simulationsDesign and analysisVerilog modellingVerification of memory modelsTest bench developmentPost silicon validationMatlab

Experience

16 yrs 4 mos

Total Experience

2 yrs 8 mos

Average Tenure

6 yrs 10 mos

Current Experience

Broadcom inc.

Principal Engineer

Jul 2019 – Present · 6 yrs 10 mos · Bengaluru Area, India

VHDLVLSIFPGAEmbedded SystemsCEmbedded Software

Mediatek

Principal Engineer

Sep 2017 – Jun 2019 · 1 yr 9 mos · Bengaluru Area, India

7nm TCAM compiler development
Design optimization and feature addition
Timing, power characterization, margin analysis
Verilog and timing model verification
Compiler coding

VerilogTiming characterizationPower characterizationMargin analysisDesign optimization

Msemi technology pvt. ltd.

Founding Member

Oct 2016 – Aug 2017 · 10 mos · Mumbai Area, India

16nm HBM2PHY IP verification
RTL verification with code coverage analysis
Gate level simulations with SDF annotation
Addition/Modification of test cases for better verification coverage and gate level simulations

RTL verificationCode coverage analysisGate level simulationsIP verification

Broadcom

Senior Staff Engineer - IC Design

Feb 2012 – Sep 2016 · 4 yrs 7 mos · Mumbai Area, India

Design and analysis of IDATA and GShare SRAM macros for 3+GHz CPU in 16nm FinFET process.
Model verification for various single and multi-port SRAM memories in 16nm FinFET process
Complete design and verification of Jitter monitor macro in 16nm and 28nm process

Design and analysisModel verificationIC Design

Netlogic microsystems

Senior Design Engineer

Dec 2010 – Feb 2012 · 1 yr 2 mos · Mumbai Area, India

Multi-Core Communications Processor chip in 28nm process:
Design and analysis of Multi-Port Register File macros
Design of digital jitter monitor and voltage monitor circuits
Verilog modelling of memory macros
Verification of memory models

Verilog modellingVerification of memory modelsDesign EngineeringMemory verification

Beceem communications

Design Engineer

Aug 2009 – Oct 2010 · 1 yr 2 mos · Bengaluru Area, India

SoC verification of dual band WiMAX/LTE baseband chip
Developed test bench for verification of Generic SPI, PCM, DMA and DDR controllers using Open Verification Methodology (OVM)
Developed generic DDR monitor using Verilog to decode the transactions on the DDR bus and record in a log file
Post silicon validation of interfaces like Generic SPI, PCM, I2C and USIM

SoC verificationTest bench developmentPost silicon validationSoC VerificationValidation