Venugopal Annavazzala — Product Manager

Design for Test (Implementation of Scan Architectures, Scan compression, ATPG verification and validation, Memory BIST, JTAG Verification, IDDQ, At-speed ATPG verification and validation), Timing analysis and closure, RTL design and coding, Test-controller implementation, Silicon debug, Product and Test Engineering support, Yield enchnacement, Specialties: Associated with first-pass silicon success of 10+ multi-million-gate chips, Strong experience with various industry standard EDA tools (like DFT-compiler, Tetramax, Fastscan/TestKompress, DFTadvisor, DC, Primetime, NCsim, Modelsim, EncounterTest, Silos fault simulator, Verdi), Verilog RTL, Verigy/Inovys Platforms, Unix/C, Perl/AWK scripting etc.

Stackforce AI infers this person is a DFT and ASIC design expert in the semiconductor industry.

Location: Hyderabad, Telangana, India

Experience: 27 yrs 6 mos