Ravishankar Menon

Software Engineer

Hyderabad, Telangana, India14 yrs 3 mos experience

Highly Stable

Key Highlights

Expert in RTL design for network accelerators
Proficient in VLSI and FPGA design methodologies
Strong background in automation and scripting

Stackforce AI infers this person is a VLSI and FPGA design expert specializing in RTL development for network applications.

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Skills

Core Skills

Rtl DesignVlsiSoftware DevelopmentVerilog

Other Skills

Very-Large-Scale Integration (VLSI)SystemVerilogPerlVHDLPCIeSchematicHardware Description LanguageTCLGNU MakeGitHubXilinxPerl ScriptStatic Timing AnalysisXilinx VivadoVitis

About

Experience in RTL development and Micro Architecture development using System Verilog, Verilog. - Currently working in implementation of PCIe application in ASIC RTL design for network accelerator card. - RTL design and implementation of Address Translation Cache in PCIe function. - Worked on Micro Architecture and RTL development of Image Signal Preprocessing blocks for AI based application. - Experience in Design Analysis and Benchmarking in Xilinx FPGA based design and Vivado software with expertise in Static Timing Analysis, Customer Design Closure, linting. - Backend manual floor-planning, placement and routing of designs on FPGA to improved timing closure and routability. - Several automation enabled using TCL, Perl, Python scripts. - Place and Route performance benchmarking and debugging in FPGA. - Familiar with Linux command line interface, Perforce version control, etc.

Experience

14 yrs 3 mos

Total Experience

3 yrs 11 mos

Average Tenure

2 yrs 4 mos

Current Experience

Chelsio communications

Member of Technical Staff

Jan 2024 – Present · 2 yrs 4 mos · Bengaluru · Hybrid

RTL development for Network Accelerators

Very-Large-Scale Integration (VLSI)SystemVerilogRTL designVLSI

Amd

2 roles

Senior Software Development Engineer

Jun 2022 – Dec 2023 · 1 yr 6 mos · Hyderabad, Telangana, India

Job Title mapped to AMD from Xilinx

PerlVerilogSoftware Development

Senior Software Engineer 1

Mar 2022 – Jun 2022 · 3 mos · Hyderabad, Telangana, India

AMD acquired Xilinx

Xilinx

3 roles

Senior Software Engineer 1

Jul 2019 – Feb 2022 · 2 yrs 7 mos · Hyderabad, Telangana, India

Software Engineer 2

Jul 2016 – Jun 2019 · 2 yrs 11 mos · Hyderabad, Telangana, India

Software Engineer 1

Mar 2014 – Jun 2016 · 2 yrs 3 mos · Hyderabad, Telangana, India

Igate

2 roles

Senior Software Engineer - VLSI

Apr 2013 – Mar 2014 · 11 mos · Pune Area, India

Promoted to Senior Engineer iGate Global Solutions Ltd. (Formerly Patni Computer Systems Ltd.).
Responsible for designing and developing RTL based IP designs in for various sub-systems on FPGA platform.
Projects include development for IPs like I2C, SPI, ARP, DHCP and also other proprietory communication protocols in Verilog and VHDL languages as an individual contributor as well as team contributor based on the project.
Development phase of design from datasheet specification to flow chart for data / design flow, architecture, RTL coding, basic test bench generation and on-board validation as a stand alone module as well as on-board validation after integration with rest of the sub-system. Board validation done on Xilinx based development board based on Virtex-5, Spartan-3 as well as customer developed board using Spartan-3, Spartan-6.

Software Engineer - VLSI

Sep 2011 – Mar 2013 · 1 yr 6 mos · Pune Area, India

VLSI RTL Design engineer at iGate Global Solutions Ltd. (Formerly Patni Computer Systems Ltd.).
Responsible for designing and developing RTL based IP designs in for various sub-systems on FPGA platform.
Projects include development for IPs like I2C, UART and also other proprietory communication protocols in Verilog and VHDL languages as an individual contributor as well as team contributor based on the project.
Development phase of design from datasheet specification to flow chart for data / design flow, architecture, RTL coding, basic test bench generation and on-board validation as a stand alone module as well as on-board validation after integration with rest of the sub-system. Board validation done on Xilinx based development board based on Virtex-5, Spartan-3 as well as customer developed board using Spartan-3, Spartan-6.