Ruchi P.

Product Engineer

India17 yrs 11 mos experience

Highly Stable

Key Highlights

Expert in RTL design and verification methodologies.
Proven track record in DDR memory controllers validation.
Strong background in semiconductor design and verification.

Stackforce AI infers this person is a Semiconductor Verification Expert with extensive experience in design validation.

Contact

Skills

Core Skills

Rtl DesignVerificationDdr Memory ControllersDesign VerificationMosfet Design

Other Skills

VerilogSystemVerilogVLSIStatic Timing AnalysisPspiceModelSimCDebuggingXilinxComputer ArchitectureCXLCache CoherencyDDRRTL simulationsSABER

Experience

17 yrs 11 mos

Total Experience

3 yrs 1 mo

Average Tenure

2 yrs 4 mos

Current Experience

Microsoft

Principal Design Verification Engineer

Dec 2023 – Present · 2 yrs 4 mos · On-site

RTL designVerilogSystemVerilogVLSIStatic Timing AnalysisPspice+6

Qualcomm

Verification Lead

Dec 2019 – Nov 2023 · 3 yrs 11 mos · Bangalore Urban, Karnataka, India

Working on
CXL.mem,CXL.cache & CHI protocol validation, Cache Coherency
DDR (LPDDR2/LPDDR5) Memory Controllers functional verification
DDR Performance Validation, Analysis and Optimization using RTL simulations

VerificationDDR Memory Controllers

Intel corporation

Design Verification Engineer

Jun 2016 – Dec 2019 · 3 yrs 6 mos · Santa Clara

Design Verification

Marvell semiconductor

2 roles

Sr.Asic Design/Verification Engineer

May 2013 – May 2016 · 3 yrs

Wireless Group

Staff Design/Verification Engineer

Mar 2013 – May 2016 · 3 yrs 2 mos

Wireless grp

Sandisk

3 roles

Sr. Design Engineer

Promoted

May 2012 – May 2013 · 1 yr · San Francisco Bay Area

Design Engineer II

Promoted

Mar 2010 – Mar 2011 · 1 yr · San Francisco Bay Area

DESIGN ENGINEER I

Jan 2008 – Mar 2010 · 2 yrs 2 mos · San Francisco Bay Area

Ministry of information technology

Intern

Jan 2004 – Jan 2005 · 1 yr

Analysis, Design, and Modeling of Sub-Threshold MOSFET” using Pspice, and SABER tools
Design of Various Biquad configurations based on Sub-threshold MOSFET using T-spice
Proposed a new “Electronics circuit block: CCII±”

Education

University of California, Santa Cruz

Certificate

Jan 2012 – Jan 2012

Stanford University

Graduate Certificate — Management Science and Engineering

Jan 2010 – Jan 2011

University of Southern California

MS — Electrical Engineering

Jan 2006 – Jan 2007

Delhi College of Engineering

BE — Electronics and Communication

Jan 2002 – Jan 2006

MGN

High School

Jan 2000 – Jan 2002

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